The laser line-width required in PSK homodyne communication systems with Dither phase-locked loop receivers are exactly evaluated. It is shown that second-order phase-locked loops require at least 0.2 pW of signal power per every Hz of laser line-width (this number refers to the system with the detector responsivity 0.94 A/W, damping ratio 0.707, and the phase error standard deviation 10°). Thi...

Active filters have proven to be more effective than passive techniques to improve power quality and to solve harmonic and power factor problems due to nonlinear loads. This paper proposes a control scheme based on the instantaneous active and reactive power. The inverter of this active filter is a three-phase, two-level converter. Space vector technique is used as modulators and pattern genera...

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...

This paper presents an all-digital phase-locked loop (PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC). It consists of an 18b Class-C digitally-controlled oscillator (DCO), 4b comparator, digital loop filter (DLF), and frequency-locked loop (FLL). Implemented in 65nm CMOS technology, the proposed PLL reaches an in-band phase noise of -112dBc/Hz and an RM...

This paper present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, sw...

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2 ) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8m CMOS technology is des...