This brief presents low-complexity detectors for a zero-IF Bluetooth receiver based on a simple phase-domain analog-to-digital converter. Measurements and simulations prove that the detectors’ sensitivity lies close to an ideal coherent Gaussian frequency-shift keying (GFSK) detector.

To dramatically reduce the need for Silicon frequency synthesizer is always measured in integer mode reproduction due to poor noise performance, a close-loop first and then measured in fractional mode. The fractional simulation platform that combines both measured and/or mode would yield the same phase noise performance when simulation results of open-loop PLL sub-blocks has been compared to th...

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-μm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and currentinjection current-mode logic (CICML) divider. A short-pulsed-reset phase fre...

Frequency-modulation atomic force microscopy (FM-AFM) relies on an accurate tracking of the resonance frequency of a scanning probe. It is now used in environments ranging from ultrahigh vacuum to aqueous solutions, for slow and for fast imaging, with probes resonating from a few kilohertz up to several megahertz. Here we present a versatile experimental setup that detects amplitude, phase, and...

A Clockand Data-Recovery (CDR) IC for a Physical Layer Controller in an Asynchronous Transfer Mode (ATM) system operating at a bit rate of 2.488Gb/s is presented. The circuit was designed and fabricated in a 0.8pm BiCMOS process featuring 13GHz fT bipolar transistors. Clock-recovery is accomplished with a Phase-Locked Loop (PLL). The PLL uses a Phaseand Frequency Detector (PFD) to increase the ...

This paper investigates a robust signal detection scheme for the uplink communication in radio frequency identification systems. An optimum maximum-likelihood sequence detector (MLSD) scheme and a sub-optimum sliding correlation detection scheme are proposed for differential bi-phase codes. The MLSD scheme has 3 dB performance improvement w.r.t. the single symbol ML detector. However, these alg...