Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

This paper explores the implementation approaches of a low power Modified Booth Multiplier (MBM) with Reduced Spurious Transition Activity Technique (RSTAT) and its application on a low power (LP) neural network. This RSTAT approach has been applied on both the compression tree of multipliers and the modified Booth Encoder to enlarge the power clampdown, for high speed and low power purposes. T...

A high speed bit-serial word-parallel finite field multiplier using redundant basis is proposed. It has been shown that the proposed architecture has higher speed compared to the previously proposed hybrid architectures using the same basis while having moderate complexity. The hybrid architecture of the proposed design provides designer the ability to set the trade off between area and delay d...

In recent years, parallel computers have changed techniques to solve problems in various kinds of fields. In parallel computers of distributed memory type, data can be shared by communication procedures called message-passing, whose speed is slower than that of computations in a processor. From a practical point of view, it is important to reduce the amount of message-passing. Domain-decomposit...

A complementary gallium-arsenide (CGaAs) 53-bit parallel array floating point multiplier is presented. The design uses Motorola's 0.5µm C-GaAs process. A conventional Wallace tree of 42 compressors is used to generate the product terms and a dynamic Ling carry select adder is utilized in the final addition to form the final mantissa. An internal latch allows the design to use a two cycle pipeli...

The MAC provides high speed multiplication with accumulative addition. In this paper, we study the various parallel MAC architectures and then implement a design of parallel MAC based on some booth encodings such as radix-4 booth encoder and some final adders such as CLA, Kogge stone adder and then compare their performance characteristics. The one most effective way to increase the speed of a ...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

The most effective way to increase the speed of a multiplier is to reduce the number of the partial products because multiplication precedes a series of additions for the partial products. To reduce the number of calculation steps for the partial products, MBA algorithm has been applied mostly where CSA has taken the role of increasing the speed to add the partial products. To increase the spee...

Digital Signal Processing (DSP) has become a very important and dynamic research area. Now-aday’s many integrated circuits are dedicated to DSP functions. Fourier Transform is widely used in industrial applications as well as in scientific research. The performance in terms of throughput of the processor is limited by the multiplication. Therefore the multiplier is optimized to make the input t...

We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. In [4], Oklobdzija et al. suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to produ...