Power reduction plays a vital role in VLSI design. Multi-bit flip-flop is an efficient method for clock power reduction. This method is to eliminate the redundant inverters by merging some flip-flops into multi-bit flip-flops. This multi-bit flip-flops can share the drive strength, dynamic power, area of the inverter chain and can even save the clock network power and facilitate the skew contro...

A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium confined between 2 Bragg reflectors forms the device. One of the Bragg reflectors is detuned from the other by making its average refractive index slightly higher, and it has a nega...

Cellular FLICE (FADD-like IL-1β-converting enzyme)-inhibitory protein (c-FLIP) is a master anti-apoptotic regulator and resistance factor that suppresses tumor necrosis factor-α (TNF-α), Fas-L, and TNF-related apoptosis-inducing ligand (TRAIL)-induced apoptosis, as well as apoptosis triggered by chemotherapy agents in malignant cells. c-FLIP is expressed as long (c-FLIP(L)), short (c-FLIP(S)), ...

A new CAD tool fREEDA based on state variable approach and universal error concept is presented for modelling and simulating systems where physical domains such as electrical, thermal, and optical interact with each other. A single implementation of device equations in fREEDA can be used with different analysis types such as transient and harmonic balance, etc. To demonstrate the multi-physics ...

In this paper, we examine the problems in the CDN of the flip flop & design an improved CDN oriented Flip-flop which is Clocked Pair Shared Flip Flop (CPSFF). Clock Division Network (CDN)’S plays an important role in the flip flop design and it’s the major element in the flip –flop for producing the logical outputs it’s much important to design the CDN with low power and area. Power consumption...