نتایج جستجو برای: on performance

تعداد نتایج: 8784153  

2010
Nikolaos Zompakis Vasileios Tsoutsouras Alexandros Bartzas Dimitrios Soudris Georgios P. Pavlos

Modern applications running on Multi-Processor Systems-on-Chip vary their workload dynamically. This gives the opportunity to the designers to perform dynamic frequency scaling (DFS). Thus the system adapts to the workload requirements of the application and increases its power efficiency. In this work, we present a DFS technique based on the workload trend of a dynamic application. The designe...

2010
Varsha Sharma Rekha Agarwal Manoj Singh Gaur Vijay Laxmi Vineetha V.

Network-on-Chip (NoC) is viewed as a viable substitution for traditional interconnection networks to achieve high performance, communication efficiency and reliability in complex VLSI architectures at deep sub micron. Achieving high performance, power efficiency with optimum area is a target for any routing algorithm in NoC. In this paper, we propose a novel routing scheme named ‘ERA’, which of...

2007
MA Liwei SUN Yihe

Network-on-chip (NoC) is a new design paradigm for system-on-chip intraconnections in the billion-transistor era. Application specific on-chip network design is essential for NoC success in this new era. This paper presents a class of source routing switches that can be used to efficiently form arbitrary network topologies and that can be optimized for various applications. Hardware description...

Journal: :Integration 2009
Seung Eun Lee Nader Bagherzadeh

Although the technology scaling has enabled designers to integrate a large number of processors onto a single chip realizing chip multi-processor (CMP), problems arising from technology scaling have made power reduction an important design issue. Since interconnection networks dissipate a significant portion of the total system power budget, it is desirable to consider interconnection network’s...

پایان نامه :وزارت علوم، تحقیقات و فناوری - دانشگاه سیستان و بلوچستان - دانشکده مهندسی برق و کامپیوتر 1391

this thesis is presented 10 ghz voltage controlled ring oscillator for high speed application. the voltage controlled ring oscillator was designed and fabricated in 0.13یm cmos technology. the oscillator is 7-stages ring oscillator with one inverter replaced by nand-gate for shutting down in the ring oscillator during idle mode. tri-state inverter was used to control of 126 bit vector in ri...

2013
Hananeh Aliee Hamid R. Zarandi Pooria M. Yaghini

This paper proposes a new methodology to design of coarse-grained routers in order to improve performance of Networks-on-Chip (NOC). In this approach, several cluster routers in region area of K×K are grouped into one new router called K2Router with similar cost of area and power, however, the performance of whole network is improved. The proposed routers are general in terms of constructions a...

2016
Ryoga Okada

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. In this thesis, we present a performance ex...

2007
M. H. Ghadiry M. Nadi D. Rahmati

Network-on-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power efficiency is the most important concern in NOC design. Routing algorithms have major effect on power and performance. We have implemented an accurate meshbased hardware model for NOC with VHDL and using it, have measured the performance and power ...

2011
Rachata Ausavarungnirun Kevin Kai-Wei Chang Chris Fallin Onur Mutlu

Higher core counts and increasing focus on energy efficiency in modern Chip Multiprocessors (CMP) have led to renewed interest in simple and energy-efficient Network-on-Chip (NoC) designs. Several recent proposed designs trade off network capacity for efficiency, based on the observation that traditional networks are overprovisioned for many workloads. Bufferless routing is one such example. Ho...

2016
Nejib Mediouni Samir Ben Abid Oussama Kallel Salem Hasnaoui Partha Pratim Pande Cristian Grecu Michael Jones Andre Ivanov Resve Saleh Graham Schelle Dirk Grunwald Andrew B Kahng Bin Li Li-Shiuan Peh Kambiz Samadi Mieszko Lis Keun Sup Shim Myong Hyon Cho Pengju Ren Omer Khan Nan Jiang Daniel U Becker George Michelogiannakis James Balfour Brian Towles David E Shaw John Kim Ruqaiya Al-Badi Maha Al-Riyami Dhiman Ghosh Prasun Ghosal Holger Blume Thorsten von Sydow Daniel Becker Kris Heid Haoyuan Ying

Network on Chips are a method of interconnecting Processing Elements, such as processors and communication controllers, through a high scalability interconnect architecture. Planning and implementing NoCs is a complex task, and simulating them at the RTL level is time consuming which has motivated the implementation of a big number of cycle accurate and behavioral simulators. In this paper, we ...

نمودار تعداد نتایج جستجو در هر سال

با کلیک روی نمودار نتایج را به سال انتشار فیلتر کنید