As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors [1][2]. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on ...

VLPW: The Very Long Packet Window Architecture for High Throughput Network-On-Chip Router Designs. (August 2011) Haiyin Gu, B.En., Zhejiang University Co-Chairs of Advisory Committee, Dr. Paul Gratz Dr. Eun Jung Kim ChipMulti-processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method...

System-on-a-chip (SoC) has emerged to become a cost-effective approach for embedded systems design with rapid advance of semiconductor technology. It allows designers to integrate a number of heterogeneous IP blocks together based on a system interconnect. However, traditional dedicated wiring as the system interconnect has many shortcomings, such as non-scalable global wire delay, failure to a...

In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting both similarities and differences between NoCs and traditional networks. As an initial case study, we examine network congestion in bufferless NoCs. We show that congestion manifests itself differently in a NoC than in a traditional network. This both reduces system throughput in c...

Chip Multiprocessor Systems (CMPs) rely on a cache coherency protocol to maintain memory access coherence between cached data and main memory. The Hammer coherency protocol is appealing as it eliminates most of the space overhead when compared to a directory protocol. However, it generates much more traffic, thus stressing the NoC and having worse performance in terms of power consumption. When...

With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of System-on-Chip(SoC) design. Network-on-Chip(NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely accepted by academe and industry. Focusing on de...

The Network-on-Chip (NoC) paradigm is currently known as an alternative solution for the on chip communication in the next SoC generation, especially, asynchronous NoCs. One of the challenges for asynchronous NoC-based systems design is testing asynchronous network architectures for manufacturing defects. To improve the testability of asynchronous NoCs, we have developed a scalable and configur...

Module-based FPGA reconfiguration offers virtualization and multitasking capabilities, but to support this, many problems need to be solved. Current methodologies are very specific and are not capable of scaling or of being reused for other applications. This thesis proposes a methodology whereby the use of dynamic reconfiguration is supported for every core independent of the communication int...

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Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-onChip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systemson-chip (SoC) design. ...