Multimode systems have emerged as an areaand power-efficient platform for implementing multiple timewise mutually exclusive digital signal processing (DSP) applications in a single hardware space. This paper presents a design methodology for integrating flexible components and controllers into primarily fixed logic multimode DSP systems, thereby increasing their overall efficiency and implement...

This paper introduces a new methodology to evaluate datapath interconnection schemes at the behavioral level. This evaluation model is validated by comparison with RTL synthesis evaluation results. It has been implemented and used for architecture exploration in order to select the best interconnection scheme to use. A generic datapath model capable of representing a variety of interconnection ...

In this paper we establish a method to obtain the stability of periodic travelling-wave solutions for equations of Korteweg–de Vries-type ut + uux − Mux = 0, with M being a general pseudodifferential operator and where p ≥ 1 is an integer. Our approach uses the theory of totally positive operators, the Poisson summation theorem, and the theory of Jacobi elliptic functions. In particular we obta...

This project proposes a method of understanding and implementing a light weighted media player using SDL based FFMPEG media player library on a SOC based board running on ARM9 hardware with LINUX as the target OS i.e., S3C2440 (also called as mini 2440) as core processor and select 1GB NandFlash as external memory. At the same time SD and USB interface are used for extending the storage. The mo...

This paper presents a jfloorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of Functional units and the schedule. The tool has combined two novel approaches: 1 A placement & Routing model to handle different architectural topologies (mux. and/ or bus based) suitable for FPGA's. 2 An e...

Power consumption of an execution unit can be reduced by interchanging its two input operands. A dynamic operand interchange method using a hardware power estimator is proposed. An efficient way to making the estimator is also described. Power reduction for multipliers is up to 29.6%. Introduction: As the need for portable systems increases, low-power design become a very important issue these ...

This talk describes a fully integrated neural recording IC with on-the-fly spike sorting and wireless telemetry. The chip consists of eight 16channel front-end blocks each consisting of amplifiers, multiplexer and ADC, data serializing circuits, DSP for on-the-fly spike sorting, digital MUX, encoder, UWB transmitter, and on-chip bias generators. The analog front end is programmable for gain, lo...

Multiplexor based Field Programmable Gate Arrays (FPGAs) are a very popular design style. However, during circuit design only limited hardware resources are available. In this paper we present an approach to multi-plexor (MUX) based circuit evolution under hardware constraints. Binary Decision Diagrams (BDDs) are used as the underlying data structure. An evolutionary technique is proposed that ...