Parallel processing is an efficient form of information processing system,which emphasizes the exploitation of concurrent events in the computing process. To achieve parallel processing it’s required to develop more capable and cost-effective systems.In order to operate more efficiently a network is required to handle large amount of traffic. Multi-stage Interconnection Network plays a vital ro...

Many downhole instrumentation tools manufacture today utilizing organic material packaging technology for producing electronic modules. Such approach with organic PCB, standard packaged discrete semiconductor and SMT-type passive components has limited the device operating temperature range in 177oC area. An alternative packaging approach is to utilize Hybrid Microelectronics Technology to incr...

We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this a...

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach usi...

This paper examines two popular prediction methods and compares the results to field data collected on Plastic Encapsulated Microcircuits (PEMs) operating in a military, airborne environment. The comparison study focused on three digital Circuit Card Assemblies (CCAs) designed primarily with plastic, surface mount parts. Predictions were completed using MIL-HDBK217 models and PRISM, the latest ...

The presented diploma thesis deals with interconnect reliability in VLSI systems from a system-level perspective. The dominant phenomena that are examined are Electromigration (EM) and Time-dependent Dielectric Breakdown (TDDB). The main goal of this work was the creation of a design flow that estimates the system’s lifetime (MTTF) because of timing failures caused by the gradual degradation of...

Step-stress accelerated degradation test (SSADT) is a useful tool for assessing the lifetime distribution of highly reliable products (under a normal-use condition) when the available test items are very few. Recently, an optimal SSADT plan has been proposed in the literature which is based on the assumption that the underlying degradation path follows a Wiener process. However, the degradation...

Soft errors arising from particle strikes to combinational logic circuits can be masked logically (by dominant inputs), electrically (the pulse is too weak to flip a node), or by opportune timing (the transient pulse arrives at a downstream latch when the latch is opaque). The latter effect—timing-window masking—is commonly approximated analytically by computing the ratio of the length of the l...

The paper presents a simulation-based study of topological characteristics of a mobile wireless ad-hoc network with unreliable nodes. The characteristics studied are connectivity, coverage, maximum inter-node distance and node degree. Knowledge of these characteristics aids in the design of new distributed protocols as well as in predicting the performance and robustness of current protocols ex...

The paper is to present a simulation method to search for an optimal (z, Z) (z < Z) values for the (z, Z) production control policy so that the expected inventory cost rate (i.e. expected total cost due to both inventory holding and backlog per unit time) is minimal for a single machine system with buffer. The system is subject to operationdependent failure only and alternates between normal an...