Three-dimensional network-on-chip (NoC) is the primary interconnection method for 3D-stacked multicore processors due to their excellent scalability and interconnect flexibility. With support of 3D NoC, non-uniform cache architecture (NUCA) commonly used organize last-level (LLC) its high capacity fast access latency. However, owing layered structure that leads longer heat dissipation paths var...

The objective of the study is to compute various reliability parameters for multi-robotic system, using Real Coded Genetic Algorithms (RCGAs) and Fuzzy Lambda-Tau Methodology (FLTM). The paper contains a new idea about the reliability analysis of robotic system. The optimal values of mean time between failures (MTBF) and mean time to repair (MTTR) are obtained using GAs. Petri Net (PN) tool is ...

Purpose – To define availability importance measures in order to calculate the criticality of each component or subsystem from the availability point of view and also to demonstrate the application of such importance measures for achieving optimal resource allocation to arrive at the best possible availability. Design/methodology/approach – In this study the availability importance measures of ...

The main effort of the present study is to analyze the availability and reliability of a high-performance linac (linear accelerator) conceived for Accelerator-Driven Systems (ADS) purpose and to suggest recommendations, in order both to meet the high operability goals and to satisfy the safety requirements dictated by the reactor system. Reliability Block Diagrams (RBD) approach has been consid...

We present ideas on how to structure software systems for high availability by considering MTTR/MTTF characteristics of components in addition to the traditional criteria, such as functionality or state sharing. Recursive restartability (RR), a recently proposed technique for achieving high availability, exploits partial restarts at various levels within complex software infrastructures to reco...

This work presents a novel approach and method for examining the characteristics of wafer-level chip-scale packages (WLCSPs) for electro migration (EM) tests. The die in the WLCSP was directly attached to the substrate via a soldered interconnect. The die shrinks area available for power and the solder bump also shrinks volume and increase quantity of electron for interconnect efficiency. The b...