In this paper we discuss evolutionary changes to FLASH to enable enhanced applications to run efficiently on both the current generation BG/P and the next generation BG/Q. We motivate the need for change by discussing current FLASH applications and the challenges they are facing on today’s architectures. Our solution to current challenges with a view to the next generation is mixed-mode MPI+Ope...

We present an efficient implementation of a Dwyer-style Delaunay triangulation algorithm that runs in O(N) expected time. An implicit quad-tree is constructed directly from the floating point bit patterns of the input points by sorting the corresponding Morton codes with a radix sorting procedure. This unique structure adapts elegantly to any (non-)uniform distribution of input points and incre...

Interest in parallel architectures applied to real time selections is growing in High Energy Physics (HEP) experiments. In this paper we describe performance measurements of Graphic Processing Units (GPUs) and Intel Many Integrated Core architecture (MIC) when applied to a typical HEP online task: the selection of events based on the trajectories of charged particles. We use as benchmark a scal...

Achieving performance through traditional techniques such as extracting more instruction level parallelism or increasing clock frequencies are losing their effectiveness due to the power wall. Multi-core processors have been put forth as a more power-performance efficient means of continuing performance scaling while coping with the realities of a power-limited design. Extrapolating the increas...

Article history: Available online xxxx a b s t r a c t Recently there is a trend to broaden the usage of lower-power embedded media processor core to build the future high-end computing machine or the supercomputer. However the embedded solution also faces the operating system (OS) design challenge which the thread invoking overhead is higher for fine-grained scientific workload, the message pa...

This memo discusses a simple many-core architecture for general-purpose computing, which is capable of the run-time adaptation towards desired corners of the performance-energy-reliability tradeoff space. In this architecture, processing cores are identical in their functional characteristics, but internally they are implemented differently in a fixed number of design styles, each optimised for...

We are seeing the advent of large scale, heterogeneous systems comprised of homogeneous general purpose cores intermingled with customized heterogeneous cores and interconnected to diverse memory hierarchies. The presence of accelerators requires support for new programming abstractions and run-time environments that can efficiently harvest platform resources comprised of general purpose and sp...

Today, there are increasingly more powerful many-core processors (MCPs) that are integrated into stationary and mobile devices, freely programmable and well suited for multimedia processing. However, there are still many obstacles and problems when programming multimedia applications for MCPs. In this paper we show that all these obstacles and problems can be solved by treating a device with an...

Many-core embedded system will integrate a large number of cores (several hundred) in order to meet the performance requirements of parallel applications. As the number of cores integrated into a chip increases, the conventional on-chip communication becomes power and performance bottleneck in many-core embedded systems. Network-on-Chip (NoC) architectures have been emerged as the most viable s...

The computing needs and the input and result datasets of modern scientific and enterprise applications are growing exponentially. To support such applications, High-Performance Computing (HPC) systems need to employ thousands of cores and innovative data management. At the same time, an emerging trend in designing HPC systems is to leverage specialized asymmetric multicores, such as IBM Cell an...