In many high-performance VLSI designs, including all recent Intel microprocessors, datapath is implemented in a bit-sliced structure to simultaneously manipulate multiple bits of data. The circuit and layout of such structures are largely kept the same for each bitslice to achieve maximal performance, higher designer productivity, and better layout density. There are very few tools available t...

Based on the Systematic Layout Planning theory and the analysis of transfer stations’ technological processes, a layout optimization model for solid waste transfer and disposal stations was made. The operating units’ layout of the solid waste transfer and disposal stations was simulated and optimized using the genetic algorithm, which could achieve reasonable technological processes, the smalle...

It is essential to accurately predict parasitics and the numerous high frequency effects while designing RF integrated circuits (RFICs). A traditional RFIC design flow involves schematic design and simulation, followed by layout, then by post-layout verification and extraction. However, this traditional flow usually leads to multiple iterations between schematic and layout designs and ends up w...

This paper browses through some well-known meta-heuristic search strategies, and briefly discusses some of their recent applications to the VLSI layout design process. It starts with very brief description of the different phases of VLSI layout design, and a brief overview of Meta-Heuristic search strategies. Since most of the VLSI layout design problems are hard optimization problems, the conc...