This paper proposes a Time Delay nonlinear dynamic model of HIV-1 (Human Immunodeficiency Virus type 1), introducing the drug consumption efficiencies as the controlling input for the model. The paper also represents the fuzzy T-S representation and the corresponding Fuzzy T-S controller. The controller parameters are tuned using LMIs (Linear Matrix Inequalities). The main focus is on the stabi...

This paper extends earlier results of wave based approach for stable force re°ecting systems in the presence of the transmission delay (constant or variable). Theoretically, stability of the whole system is kept for any time delay, but degradation performance increases proportionally with a large delays. In this paper, we propose a new control scheme that is also based on wave variables, but mi...

Abstmct-The effect that large Propagation delay has on the problem of network access is explored for the infinite population model with success-idle-collision feedback information, where the feedback information suffers a large propagation d&y N. A simple lower bound is given on the PrObeMlity that a packet is not successfully transmitted within N / 2 time units (not including the fomrd propaga...

In this paper, the time domain waveform is approximated for calculation of delay, rise, settling time, damping ratio and natural frequency of a second order RLCG on-chip VLSI interconnect line. It can also be evaluated for multiple interconnect systems but due to harmonics higher order systems are ignored. The model is applied to a single RLCG interconnect line which can also be extended for mu...

This paper presents an electronic system that extracts the periodicity of a sound. It uses three analog VLSI building blocks: a silicon cochlea, two Inner Hair Cell circuits and two spiking neuron chips. The silicon cochlea consists of a cascade of filters which delays (and filters) the input sound as it passes along the cascade. The time delay added by each individual filter in the cochlea inc...

1. Introduction: As digital Integrated Circuits (ICs) are driven at higher and higher clock frequencies, the need for a better clock net routing scheme has become essential. For complex ASICs (or VLSI), circuit designers ensure proper timing by carefully planning and implementing the distribution of clocks throughout the circuit. This part of the design process is critical because poor clock di...