The problem of ordering and sizing parallel wires residing in a single metal layer within an interconnect channel is addressed in this paper. Wires are ordered such that cross-capacitances between neighboring wires are optimally shared for circuit delay minimization. Using an Elmore delay model including cross capacitances, an optimal wire ordering is uniquely determined, such that average sign...

Crosstalk in VLSI interconnects is a major constrain in DSM and UDSM technology. Among various strategies followed for its minimization, shield insertion between Aggressor and Victim is one of the prominent options. This paper analyzes the extent of crosstalk in inductively coupled interconnects and minimizes the same through distributed shield insertion. Comparison is drawn between signal volt...

N-digit, radix-a bases are proposed for VLSI implementation of redundant arithmetic, mod m, where a m = ±1, a j m π ±1, for 0 < j < N and m is prime. These bases simplify arithmetic overflow and are well suited to redundant arithmetic. The representations provide competitive, multiplierless T-point Number Theoretic Transforms, mod m, where T | N or T | 2N.

VLSI design does not stand alone. The challenges and opportunities for the design community are driven and shaped by larger forces, from semiconductor technology evolution through product trends, and ultimately to large scale societal forces which are far beyond the control of designers. To understand the requirements for design, then, we first need to examine the larger environment in which we...

In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148-159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.

Abstract In this paper, we extend our generalized methodology for designing lower-error area-efficient fixed-width two’s-complement multipliers that receive two s -bit numbers and produce an s -bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to lower-error fixed-width m...