The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique fo...

Advantages are shown by using the DSP for the real time online control of hydraulic axis. The interrupt latency time is the most important factor for equidistant position samples to control the velocity as accurately as possible. The trajectory calculations for the velocity and position are presented as well as their derivation for Scurvatures. The control of the velocity, as a function of the ...

Servando López-Aguayo, Yaroslav V. Kartashov, Victor A. Vysloukh, and Lluis Torner ICFO-Institut de Ciencies Fotoniques, and Universitat Politecnica de Catalunya, Mediterranean Technology Park, 08860 Castelldefels (Barcelona), Spain Photonics and Mathematical Optics Group, Tecnólogico de Monterrey, Monterrey México 64849 Departamento de Fisica y Matematicas, Universidad de las Americas – Puebla...

This paper presents a fast and eeective linear intraprocedu-ral register allocation strategy that optimizes register usage across procedure calls. It capitalizes on our observation that while procedures that do not contain calls (syntactic leaf routines) account for under one third of all procedure activations , procedures that actually make no calls (eeective leaf routines) account for over tw...

Retrieval from semantic memory is usually considered within a time window around 300-600ms. Here we suggest that lexical access already occurs at around 100ms. This interpretation is based on the finding that semantically rich and frequent words exhibit a significantly shorter topographical latency difference between the site with the shortest P1 latency (leading site) and that with the longest...