In this paper we show the possibility of using FAUST (a programming language for function based block oriented programming) to create a fast audio processor in a single chip FPGA environment. The produced VHDL code is embedded in the on-chip processor system and utilizes the FPGA fabric for parallel processing. For the purpose of implementing and testing the code a complete System-On-Chip frame...

Failures will be occur inevitably because Wireless Sensor Networks (WSNs) are randomly deployed in a hostile nature environment. Therefore, considering faults in WSNs is essential when we design WSN. In this paper, a SEC-DED (Single Error Correcting-Double Error Detecting) code and the implementing method is presented. Proposed code scheme is suitable for the WSN. Also, this paper classifies fa...

Business processes and business rules are implemented in almost all enterprise systems. Approaches used today to their implementation are very sensitive to changes. In the paper authors propose to separate business logic layer from business rule layer by introducing an integration layer. The connections between both parts are expressed in a dedicated domain specific language (DSL). The definiti...

We describe a novel technique for code selection based on data ow graphs which arise naturally in the domain of digital signal processing Code selection is the optimized mapping of abstract opera tions to partial machine instructions The presented method performs an important task within the retargetable microcode generator CBC which was designed to cope with the requirements arising in the con...

Programs that are not loop intensive and which have small basic blocks present a challenge to architectures that rely on instruction level parallelism to deliver high performance. This paper presents a heuristic for moving operations across basic block boundaries based on profile information gathered from previous executions of a program. Architectural support is required for executing these op...

This paper, partly tutorial in nature, describes an approach to the implementation of the 4.567 kbps TETRA speech codec on the TMS320C54x DSP family. The TETRA system is introduced and its speech codec is described in detail. The TETRA standard describes the speech codec in bit-exact, fixed-point C-code. Our paper compares the efficiency of implementing this code by first writing it in C and cr...

We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in th...

DYLP is a linear programming code implementing a dynamic simplex algorithm similar to that outlined by Padberg in [5]. The code attempts to maintain a reduced active constraint system by regularly purging loose constraints and variables with unfavourable reduced costs, and adding violated constraints and variables with favourable reduced costs. In abstract, the code alternates between primal an...

The paper presents a scheme of code generation for vector expressions implemented in the CC] compiler (CC] is a vector ANSI C superset aimed at vector and superscalar architectures). The scheme is based on two well-known optimization techniques { loop invariant code motion and iteration space tiling. The problem of nding the optimal tile size for the imperfectly nested loop system implementing ...