Recently, numerous watermarking-based techniques for intellectual property protection of DSP artifacts, such as images, compressed and uncompressed audio and video data, and text documents have been proposed. However, the applicability of all techniques proposed until now are limited to digital data and they either implicitly or explicitly exploit the imperfection of human perception to audio a...

Applications that leverage the dynamic partial reconfigurability of modern FPGAs are few, owing in large part to the lack of suitable tools and techniques to create them. While the trend in digital design is towards higher levels of design abstractions, forgoing hardware description languages in some cases for high-level languages, the development of a reconfigurable design requires developers ...

Modern DSPs are low cost and have integral communications, encouraging their use in large parallel systems. E ective software methods are critical to the success of this trend. A model-based program synthesis approach has been proven e ective for developing large parallel instrumentation systems. This paper describes an essential component of this approach, the low level kernel. The kernel has ...

We introduce a high-level synthesis methodology to automatically synthesize asynchronous circuits from a concurrent language called ALEPH. ALEPH is a high-level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation, and communication. This specification is translated into a Petri net which has actions. These actions are refined t...

This work has attempted to exploit information sharing to improve the results of Adaptive Simulated Annealing [1] as an optimization algorithm of the high-level synthesis of testable data paths. We have used Messengers [3] as a coordination tool to run several parallel instances of the annealing algorithm on the same design with di erent probability arrays for the perturbations. When all these ...

A Unified Lower Bound Estimation Technique for High-Level Synthesis The importance of effective lower bound estimation (LBE) techniques is well-established in HighLevel Synthesis (HLS), since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of previous work has focuse...

Scenario-based specifications such as Message Sequence Charts (MSCs) are useful as part of a requirements specification. A scenario is a partial story, describing how system components, the environment, and users work concurrently and interact in order to provide system level functionality. Scenarios need to be combined to provide a more complete description of system behavior. Consequently, sc...

In the high-level synthesis domain, the integration of user defined RT components in the algorithmic specification plays an important role. The implementation of VHDL models emulating specific functional and timing behavior at the algorithmic level is expensive and time-consuming. Moreover, particular functional and timing behavior can only be implemented at the RT level, e.g. interrupt handlin...