Floating point arithmetic is widely used in many areas especially scientific computation and signal processing. The main objective of this paper is to reduce the power consumption and to increase the speed of execution and the implementation of floating point multiplier using sequential processing on the reconfigurable hardwareFloating Point (FP) addition, subtraction and multiplication are wid...

Multiple constant multiplication (MCM) scheme is widely used for implementing transposed direct-form FIR filters. While the research focus of MCM has been on more effective common subexpression elimination, the optimization of addertrees, which sum up the computed sub-expressions for each coefficient, is largely omitted. In this paper, we have identified the resource minimization problem in the...

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) usin...

The control of biochemical processes is a major goal in systems and synthetic biology. Current approaches are based on ad-hoc designs, whereas a general and modular framework would be highly desirable, in order to exploit the well-assessed methods of control theory. A well-known problem when dealing with complex biosystems is represented by the retroactivity effect, which can significantly modi...

The ADC architecture and timing diagram are shown in Figure 1. The converter consists of a 7b coarse flash stage, a 7b digital-to-analog converter (DAC), a subtractor. and a 6b fine flash stage. One-of-n decoders and ROhIs are used to convert the thermometer code outputs ofthe two flash stages to binarydata, that is thencorrecteddigitally to produce the final output. One bit ofredundancy. or ov...

This paper describes a framework and tools for automating the production of designs which can be partially recon gured at run time. The tools include: (i) a partial evaluator, which produces con guration les for a given design, where the number of con gurations can be minimised by a process known as compile-time sequencing; (ii) an incremental con guration calculator, which takes the output of ...

This paper presents a novel (low arithmetic unit count) hardware architecture for performing lifting-based JPEG2000's 513 Discrete Wavelet Transform (DWT). The architecture is built around parallel Shift-Accumulator Arithmetic Logic Units (ALUs) which can encode (with implicit embedded extension[S]) up to five levels of transformation. The proposed architecture, which consists of three adders, ...

A class of complementary IIR filters is introduced. One of these filters can be realized as a tapped cascaded interconnection of identical allpass subfilters. The complementary filter is then obtained automatically by adding some extra allpass subfilters and a subtractor. The proposed filters are always allpass complementary and, under certain conditions, also magnitude complementary. Further, ...

[email protected] 1 , [email protected] 2 , Abstract—the most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. Addition is a fundamental arithmetic operation and it is the base for arithmetic operations such as multiplication and the basic adder cell can be modified to function as subtractor by adding ano...

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due correspondence between features of QCA circuits. This work aims push forward state-of-the-art QCA-based circuits implementation by proposing a novel full adder\full subtractor (FA\FS). At fir...