Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/ divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design base...

This project presents two original implementations of improved accuracy current-mode multiplier and divider circuits. Besides the advantage of their simplicity, these original multiplier and divider structures present the advantage of very small linearity errors that can be obtained as a result of the proposed design techniques (0.9% and 0.75%, respectively, for an extended range of the input c...

A simple and analytical design methodology for a novel multi-way Bagley Polygon power divider with arbitrary complex terminated impedances is proposed in this paper. The design parameters including electrical lengths and characteristic impedances can be obtained by the provided closed-form mathematical expressions when complex terminated impedances are known. Moreover, for convenient test, we d...

In recent years, high-speed communication systems beyond 10Gb/s have been realized in CMOS technology. A 40Gb/s transmitter including the MUX has been developed in 0.13μm CMOS [1], and a 40Gb/s MUX/DEMUX in 90nm CMOS has been reported [2]. These circuits extend the bandwidth with inductive peaking for 40Gb/s operation. They use supply voltages that exceed the logic supplies used in these techno...

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the o...