Continued research into the development of III–V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which beco...

In this paper, we describe our oating-gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many eeects inherent in these processes. We add oating-gate charge by electron tunneling, and we remove oating-gate charge by hot-electron injection. With this oating-gate technology...

Dual Metal Gate (DMG) technology was proposed to reduce the short channel effects (SCE’s) of double gate MOSFETs. But, DMG alone is not enough to rectify the problem of gate tunneling current due to thinning of oxide layer with device downscaling. So, the use of high-k dielectric as gate oxide is considered to overcome the gate tunneling effect. But, high gate dielectric thickness leads to high...

Optimizing gate scheduling at airports is an old, but also a broad problem. The main purpose of this problem is to find an assignment for the flights arriving at and departing from an airport, while satisfying a set of constraints.A closer look at the literature in this research line shows thatin almost all studies airport gate processing time has been considered as a fix parameter. In this res...

Reversible logic has attracted significant attention in recent years. It has applications in low power CMOS, quantum computing, nanotechnology, and optical computing. Traditional gates such as AND, OR, and EXOR are not reversible. In fact NOT is the only reversible gate from the traditional set of gates. Several reversible gates have been proposed. Among them are the controlled NOT (also known ...