Th is paper presents a programmable resistor using two-input floating gate MOS transistor (FGMOST). One of the two-input gates is connected to the drain and the other is connected to a tuned voltage to control the floatin g gate transistor resistance. A wide range of the programmable resistance is achieved by controlling the tuned voltage. The resistance is changed by 33% by varying the tuned v...

This paper presents a design of the transimpedance amplifier using 0.35μm CMOS technology. In the proposed transimpedance amplifier, feedback resistor RF of conventional transimpedance amplifier has been replaced by NMOS transistor as an active feedback resistor. This circuit operates at 3.3V power supply voltage and for a photocurrent of 0.5μA.The proposed transimpedance amplifier having low n...

Using measured capacitance-voltage curves with different gate lengths and current-voltage characteristics at low drain-to-source voltage for the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) of different drain-to-source distances, we found that the dominant scattering mechanism in AlGaN/AlN/GaN HFETs is determined by the ratio of gate length to drain-to-source distance. For dev...

A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and >...

Nanoscale superconductor/semiconductor hybrid devices are assembled from indium arsenide semiconductor nanowires individually contacted by aluminum-based superconductor electrodes. Below 1 kelvin, the high transparency of the contacts gives rise to proximity-induced superconductivity. The nanowires form superconducting weak links operating as mesoscopic Josephson junctions with electrically tun...

The effect of impact ionization on pseudomorphic high electron mobility transistors is studied using Monte Carlo simulations when these devices are scaled into deep decanano dimensions. The scaling of devices with gate lengths of 120, 90, 70, 50 and 30 nm has been performed in both lateral and vertical directions. The impact ionization is treated as an additional scattering mechamism in the Mon...

In this paper, the threshold voltage of fully depleted silicon on insulator device with geometry scale down below 100nm is investigated deeply. All the device simulations are performed using SILVACO Atlas device simulator. Several ways to control the threshold voltage are proposed and simulated. Threshold voltage changing with the silicon film thickness, channel doping concentration, gate oxide...

We report integrated charge sensing measurements on a Si/SiGe double quantum dot. The quantum dot is shown to be tunable from a single, large dot to a well-isolated double dot. Charge sensing measurements enable the extraction of the tunnel coupling t between the quantum dots as a function of the voltage on the top gates defining the device. Control of the voltage on a single such gate tunes th...

Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% w...

The present understanding of wear-out and breakdown in ultrathin ( 5 0 nm) SiO2 gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of de...