fault tolerance is one of the important issues in industries, such as transportation, military, chemical and nuclear sectors. reliability and safety are two vital attributes of fault tolerant systems, and redundancy is a common way to improve these parameters. this article studies the impact of including cold standby spares in system architecture. to do this, it uses the markov model of the sys...

Partial detectability profiles are formed by randomly sampling each fault's detectability and are used in estimating the fault coverage of random input test vectors on combinational circuits. Partial detectability profiles are particularly useful for predicting fault coverage for large circuits with a large number of inputs. Predictions made using full and partial detectability profiles are com...

We study the coverage problem for sensor networks from the fault tolerance and reliability point of view. Fault tolerance is a critical issue for sensors deployed in places where they are not easily replaceable, repairable and rechargeable. Failure of one node should not incapacitate the entire network. We propose three 1-fault tolerant topologies, namely square, hexagonal and improved 8-node. ...

This paper presents an experimental study of the fault sensitivity of four programs included in the MiBench test suit. We investigate their fault sensitivity with respect to hardware faults that manifest as single bit flips in main memory locations and instruction set architecture registers. To this end, we have conducted extensive fault injection experiments with two versions of each program, ...

The paper suggests test derivation approaches to obtain test suites for concurrent systems based on the concept of fault coverage criteria in opposition to structural test coverage criteria. Using a partial-order model, called Mazurkiewicz Trace Machine (MTM), for test derivation, the state explosion problem can be alleviated. The derived test suites are characterized by their small size compar...

Current work presents a set of fault models allowing high coverage for sequential cores in Systems-on-aChip. We propose a novel approach combining a hierarchical fault model for functional blocks, a functional fault model for multiplexers and a mixed hierarchical-functional fault model for comparison operators, respectively. The fault models are integrated into a fast high-level decision diagra...

Debugging software is a difficult and timeconsuming work. Fault localization techniques are becoming extremely important. Coverage Based Fault Localization (CBFL) is very commonly used in fault location technique. Tarantula is a typical one. It uses the coverage statistics of failed execution paths and passed execution paths to calculate the suspiciousness in the software. However, since this t...

FPGA Design for Decimeter Scale Integration (DMSI) p. 64 Process Variations and their Impact on Circuit Operation p. 73 Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits p. 84 Characterization of CMOS Defects Using Transient Signal Analysis p. 93 Accurate Fault Modeling and Fault Simulation of Resistive Bridges p. 102 Functional Verification Coverage vs. Physical Stuck-at Fault...

Coverage conservation and extend the network lifetime are the primary issues in wireless sensor networks. Due to the large variety of applications, coverage is focus to a wide range of interpretations. The applications necessitate that each point in the area is observed by only one sensor while other applications may require that each point is enclosed by at least sensors (n>1) to achieve fault...

A logic coverage measure related to MC/DC testing is used to estimate residual faults. The residual fault prediction method is evaluated on an industrial PLC logic example. A randomized form of MC/DC testing is used to maximize coverage growth and fault detection efficiency.