This paper proposes an improved control method based on modified Delta-Sigma Modulator (DSM) to enhance transient response and improve harmonic contents of buck DC-DC converter. The main advantages of the proposed method are improving the output voltage frequency spectrum, correction of the output voltage harmonic contents and sideband harmonics, reduction of switching noise peaks at the output...

This paper describes the design and implementation of a low power reconfigurable sigma-delta modulator for multi-standard wireless applications in a 90-nm CMOS technology. Both architectural and circuital reconfigurations are used to adapt the performance of the modulator to five different communication standards. The feasibility of the proposed solution is shown using the system-level simulati...

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25m 1P5M CMOS process with MIM ca...

Oversampling techniques offer several advantages for the implementation of high-resolution analog-to-digital (A/D) converters in VLSI technologies. This paper examines the application of oversampling techniques to A/D conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (2A) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding s...

This paper describes the design and implementation of a recon ̄gurable low-power sigma-delta modulator (SDM) for multi-standard wireless communications in a 90 nm CMOS technology. Both architectural and circuital recon ̄gurations are used to adapt the performance of the modulator to multi-standard applications. The feasibility of the presented solution is demonstrated using system-level simulatio...

An 8th-order continuous-time (CT) bandpass delta-sigma (AZ) modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signalto-noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order...

A novel application and generalization of sigma–delta ( ) modulation has emerged in three-phase power-electronic converters. A conventional modulator with scalar signals and binary quantizer is generalized to a modulator with vector signals and a hexagonal quantizer. Indeed, power-electronic switching states may be thought of as determining the quantizer outputs. The output spectrum is a key pe...

This article focuses on the in-phase/quadrature (I/Q) imbalance problem in quadrature ΣΔ modulators (QΣΔM). In the literature, such quadrature modulators have been seen as a promising possibility for software defined radio (SDR) receivers, but matching the quadrature circuits is an inevitable problem for this kind of systems. In this article, an analytic closed-form model will be derived for a ...