This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz ...

This paper presents a Variable Latency (VL) adder. It is introduced to work at a lower time delay than that required by a Ripple Carry Adder (RCA). It proposes a new technique called HOLD LOGIC. The VL-adder design is further modified to overcome the effects of negative bias temperature instability (NBTI). In the CLDC (Carry Length Detection Circuit), more number of components are used and it p...

This paper presents the design of low power and high speed circuit using a new CMOS logic family called feedthrough logic. FTL arithmetic circuits provides for smaller propagation time delay when compared with the standard CMOS technologies. The proposed circuit has very low dynamic power consumption and lower propagation delay compared to the recently proposed circuit techniques for the dynami...

Low power and high speed digital circuits are basic needs for any of digital circuit; De-multiplexer is a basic circuit for any digital circuit. In this paper demultiplexer has been designed using CMOS, transmission gate pseudo nmos logic. The performance of designs has been compared in terms of power consumption, delay and transistor counts. The proposed design demonstrates the superiority in ...

Fast delay estimation methods, as compared to simulation techniques, are needed for incremental performance-driven layout synthesis. On-chip inductive and conductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speeds; circuit complexity and interconnect lengths. Inductance causes noise in the signal waveforms, which can adversely affect the per...

Two-pattern test is required to identify delay faults in a circuit. The importance of delay fault testing is increasing gradually because of the fact that traditional stuck-at fault testing is failing to guarantee an acceptable quality level for today’s high-speed chips. Some defects and/or random process variation do not change the steady state behavior of a circuit but affect the at speed per...

Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We present a longest path theorem at the module level of abstrac...

Delay elements are basic building blocks of clock distribution network in VLSI circuits and systems. They are intended to define a time reference for the movement of data within those systems. In this paper, we describe an efficient structure of a linear current starved delay element. The proposal is based on modification of the bias circuit. Thanks to this modification, an improved linearity i...

A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption, positive edge triggered conventional Delay (D) flip-flop can be designed for increasing the speed of counter in Phase locked loop, using 32nm CMOS technology. The conventional D flip-flop has higher operating frequencies but it features static power dissipation. The designed counter can be used in the divid...