IDDQ test-based outlier rejection becomes difficult for deep sub-micron technology chips due to increased leakage and process variations. The use of Neighbor Current Ratio (NCR) that uses wafer-level spatial correlation for identifying outlier chips has been proposed earlier as a means of coping with these issues. Due to the slow speed of IDDQ test, there is a strong motivation to reduce the nu...

With an increase in the number of transistors on-chip, the complexity of the system also increases. In order to cope with the growing interconnect infrastructure, the “Network on chip (NoC)” concept was introduced. With network methodologies coming on-chip, various characteristics of traditional networks come into play. So far, failures that are common in regular networks were hardly considered...

As deep-sub-micron and beyond technology emerges, quality assurance of microelectronic circuits and systems becomes more important than ever. Consequentially, (1) a strong need for well-educated microelectronic circuits and systems test engineers is desired by the industry, (2) graduate-level research efforts are also called to overcome numerous microelectronic circuits and systems test issues....

We detail the design of a scalable infrastructure, called Paradys, developed for parallel circuit simulation. Early measurements of its scalability (some 0.9x of parallel efficiency) are encouraging signs to measure on larger parallel configurations as well as to envision its application for simulation of deep sub-micron technology. This good scalability is, in great part, achieved thanks to a ...

The study of wafer level hermetic bonding using sub-micron gold particles with the mean diameter of 0.3_m was conducted at bonding temperature of 150 – 300 °C with varying bonding pressure in the range of 50 – 100 MPa. 4.5 mm-square, 10 μm – 100 μm-wide seal line patterns of sub-micron Au particles were formed on Si or glass wafers by means of wafer level processing using photolithography and s...

A high DC-gain low-power current recycling amplifier using positive-feedback technique is presented. In the proposed amplifier, the positive-feedback signal used to enhance the DC-gain is derived from the extra nodes created by cascoding. Positive-feedback offers the ability of obtaining a very high DC-gain, ideally infinite gain, without affecting high frequency performance and stability. Unde...

Project funded by the European Community under the " Information Society Technologies " Programme (1998-2002)

E merging technology trends are gravitating towards extremely high levels of integration at the package and chip levels, and use of deeply scaled technology in nanometer, approaching 10nm CMOS. Challenges will arise due to the ability to design complex systems such as robots that encompass sensors, transducers, communications systems and processors, all of which require memory devices, and are ...

Our life is filled by various modern electronic products. Semiconductor memories are essential parts of these products and have been growing in performance and density in accordance with Moore’s law like all silicon technology. The process technology has been scaling down from last two decades and to get the functional and high yielding design beyond 100-nm feature sizes the existing design app...