Polymer solar cells (PSCs) with different anode buffer layers were fabricated to investigate dipoleassisted hole extraction on the performance improvement of PSCs. The power conversion efficiency (PCE) of PSCs was increased from 4.77% to 6.18% with 29.6% improvement due to the increased short circuit current density (Jsc) from 12.00 to 15.65 mA/cm 2 induced by the oriented LiF dipole-assisted h...

The typical description of a VLSI layout is the geometrical description of masks. Layout verification [4] is the testing of a layout to see if it satisfies design and layout rules. An important problem in layout verification is layout device extraction, which involves detection of capacitors, resistors, transistors etc. from the geometrical description of masks. The layout extraction process st...

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime....

In this paper we address the chip-level thermal simulation problem. Our work is based on some early results treating electro-thermal problems on circuit level 11, 22. The developed electro-thermal simulation package has been integrated under Cadence DFWII Opus. Due to its relatively low CPU need this package can be used as a thermal veriication tool of layouts of analog circuits. In our approac...

Bridging fault extraction and analysis are crucial to deriving high quality bridging fault test generation. As state-of-the-art designs integrate millions of logic gates into a VLSI circuit, a run-time and memory eecient bridging fault extraction approach must be developed to cope with the design complexity. In this paper, a hierarchical bridging fault analyzer-FAULTAN is described. In FAULTAN,...

Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires the extraction of a gate-level (logic) model from the transistor level representation of the circuit under test. Logic extraction is an error prone process due to extraction tool limitations and due to the human interf...

The quality of image segmentation is often affected b y that of edge profile extracted from a target image. The completely closed and continuous edge for a target object is preferable, but it is actually dificult to obtain such a perfect edge. This paper thus proposes a novel technique for broken edge linking and edge enhancement based on an i d e a of electronic-circuit simulation, and applies...

This paper provides an effective method for parameter extraction of microelectronic devices and elements. A novel method, memetic differential evolution (MDE) algorithm, is proposed in this paper. By combining differential evolution (DE) algorithm, mutations in immune algorithm (IA), and special operators for parameter extraction, MDE possesses characteristics of high accuracy, stability, gener...

Charge separation and extraction dynamics were investigated in high-performance bulk heterojunction solar cells made from the polymer PTB7 and the soluble fullerene PC71BM on a broad time scale from subpicosecond to microseconds using ultrafast optical probing of carrier drift and the integral-mode photocurrent measurements. We show that the short circuit current is determined by the separation...

This paper presents a novel optical-electronic shape recognition system based on synergetic associative memory. Our shape recognition system is composed of two parts: the first one is feature extraction system (FES); the second is synergetic pattern recognition system (SPRS). Hough transform is proposed for feature extraction of unrecognized object, with the effects of reducing dimensions and f...