In this paper, a design of an unequal split Wilkinson power divider (WPD), with high power split ratio, using non-uniform transmission lines (NTLs) is presented. The design is based on using NTLs in each branch of the divider instead of the conventional uniform ones. Besides the achievement of high power split ratio, the size of the designed WPD is reduced. The design procedure is presented for...

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

We evaluated the performance of three CMOS current-mode, multivalued adder circuits in terms of area (reduced interconnect), speed, and power consumption and compared them to their binary, voltagemode counterparts. We present the simulation results of these circuits, and one new circuit which has fewer transistors than any voltage-mode full adder. Our results, however, show that while current-m...

SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix-2 and radix-4. Higher radix dividers are therefore formed by a combination of low-radix stages. In this paper, we present an analysis of the effects of radix-2 and radix-4 SRT divider ...

This paper presents a design of 48 GHz CMOS phase-locked loop (PLL) for 60 millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, fundamental PLL with quadrature clock generation scheme is proposed. Specifically, an implicit capacitive-bridged shunt peaking network, second order harmonic filtering technique realized in volta...

In this paper a new synthesis for circuit design of Euclidean distance calculation is presented. The circuit is implemented based on a simple two-quadrant squarer/divider block. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak inversion region, features low circuit complexity, low power (<20uW), low supply voltage (0.5V), two quadrant input current, wide dyn...

The Low Current Pulser generates up to a 30 kV potential difference between the wire holder’s anode and cathode. This voltage drops across the specimen and is supported by a combination of the wire’s resistance and the holder’s inductance. A typical load may have 2Ω resistance and 50 nH inductance. Voltage and current are measured with each shot. Current is recorded using a rogowski coil and vo...

This paper is focused on how to implement a nonlinear voltage divider used in the electrical power network disturbances measurement system preconditioning circuit. The voltages acquired from the electrical power network have amplitudes between 0.2 kV and 10 kV, values which are very high for an acquisition board. These amplitudes must be reduced to the values accepted by the acquisition boards:...