A novel circuit model based on a trainable memristorcrossbar network integrated with a CMOS circuit for pattern classification and recognition is proposed and analyzed in this paper. The configurable memristors along each column wires of the crossbar are trained by a standard pattern input from the row wires of the crossbar to represent the pattern. After the training, the crossbar network can ...

This paper deals with the design of novel sub-1-V bandgap reference circuit using only MOS transistors in 0.18 μm CMOS technology, for a supply voltage of 1.8V. The circuit produces a voltage reference of 466.5 mV at 27C with a temperature coefficient of 28.4 ppm/C in the range of -20 to +120C. The power supply rejection of circuit is -30 dB at 8 KHz and this rejection further increase to -50 d...

We have investigated a chaotic circuit utilizing CMOS ring oscillators[1]. The circuit consists of two CMOS ring oscillators and two diodes. A CMOS ring oscillator is used for CMOS process performance test. This oscillator consists of a series of inverter circuits. It has a very simple structure. Therefore, we consider that the proposed circuit is realized very easily. In the past studies, we h...

This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical s...

A novel high-speed and low-voltage CMOS level shifter circuit is proposed. The proposed circuit is suitable for block-level dynamic voltage and frequency scaling (DVFS) environment or multiple-clock and multiple-power-domain logic blocks. In order to achieve high performance in a chip consisting of logic blocks having different VDD voltages, the proposed circuit uses the circuit techniques to r...

A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 μm HP CMOS process. A single neuron cell occupies only 0.0076 mm2, which represents an area smaller than the one occupied by a standard bonding pad. The...

We present in this paper an overview of circuit techniques dedicated to design reliable low-voltage (1-V and below) analog functions in deep submicron standard CMOS processes. The challenges of designing such low-voltage and reliable analog building blocks are addressed both at circuit and physical layout levels. State-ofthe-art circuit topologies and techniques (input level shifting, bulk and ...

This paper present high-precision half-wave rectifier circuit in dual phase output mode by 0.5 μm CMOS technology, + 1.5 V low voltage, it has received input signal and sent output current signal, respond in high frequency. The main structure compound with CMOS inverter circuit, common source circuit, and current mirror circuit. Simulation and confirmation quality of working by PSpice program, ...

Abstrac t  As Complementary Metal-Oxide-Silicon (CMOS) technology scales its critical dimensions, it imposes negative impacts on digital circuit performance mainly in two aspects: leakage and variability. It is widely believed that Static Random Access Memory (SRAM), among all digital circuits, is most susceptible to these impacts. Attempting to accommodate leakage and process variability in a...

A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Three-valued modeling, where the third state indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete verificati...