In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit ...

A large number of energy recovery circuits have been described to reduce the power consumption of CMOS logic circuits. Many of these circuits use diode connected transistors, accurately timed multiple clocks and self resonating power clocks. Boost logic is a 2 phase high speed energy recovery family that voltage scaling and high gate overdrive to achieve highly efficient energy recovery. In thi...

 A new adiabatic CMOS logic that operates from a single-phase power-clock is presented. A simple and efficient power-clock generator is integrated with the logic to generate the required AC power-clock supply waveform. Circuit performance is evaluated using a chain of inverters realized in 1.2μm technology. Experimental results show energy savings comparable to other adiabatic logic families t...

Introduction: Current-mode logic (CML) circuits are widely used in many high-speed and high-performance applications [1]. The differential topology of CML circuits provides high immunity to supply noise and crosstalk, while reduced voltage swing at the output helps to operate the circuit in very high frequencies with low noise generation [1, 2]. These properties make the MOS CML (MCML) topology...

Level shifters play critical roles in ultra low-voltage circuits and systems. a new low power level shifter (LS) is presented for robust logic voltage shifting from near/sub threshold to above threshold domain. The new circuit combines the multi threshold CMOS technique along with novel topological modifications to guarantee a wide voltage conversion range with limited static power and total en...

---------------------------------------------------------------------***--------------------------------------------------------------------Abstract Double-tail comparator is basically designed for SAR-ADC in order to optimize the power with which the circuit operates on high-speed. The circuit is designed under 90 nm CMOS technology means by reducing the technology the parameters get also redu...

The secret information, which is embedded in integrated circuit (IC) devices such as a smart card, has the risk of theft by reverse engineering (RE). The circuit design of IC can be stolen by the RE, and the counterfeit can be illegally fabricated. Therefore, the secure IC device requires the circuit architecture protected from the RE attacks. This paper proposes the diffusion programmable devi...

| A new logic family, Diierential Current Switch Logic (DCSL) for implementing clocked CMOS circuits has been developed. DCSL is in principle a clocked diieren-tial cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better perform...

Shorts and opens are the most common types of catastrophic defects in today's CMOS ICs. In this paper we show that an open in the interconnect wiring of a digital CMOS circuit, which permanently disconnects inputs of logic gates from their driver, can cause oscillation or sequential behavior. We present supporting experimental data collected by creating an interconnect open in a manufactured ch...

AbstructDifferential current switch logic (DCSL), a new logic ihmily for implementing clocked CMOS circuits, has been developed. DCSL is in principle a clocked differential cascode voltage switch logic circuit (DCVS). The circuit topology outlines a generic method for reducing internal node swings in clocked DCVS logic circuits. In comparison to other forms of clocked DCVS, DCSL achieves better...