,/ This paper models high-speed VLSI interconnects by using a generic distributed RLC-tree. Through a detailed analysis of the distributed RLC-tree a two-pole approximation system is consequently established to formulate the performance-driven layout in MCM designs. An in-depth study of the formulated performance-driven layout problem reveals the interplay between the interconnector's performan...

This Application Note originally started as a “cook book” for a true 12-bit layout. The assumption of this type of approach is that a reference design could be provided, which easily could be used for every layout implementation. But, the notion of this approach is fairly unrealistic. There are a multitude of successful ways to layout out systems with 12-bit Analog-to-Digital (A/D) Converters a...

This paper presents the design and implementation of a rectifier for piezoelectric energy harvesting based on the parallel-synchronized-switch harvesting-on-inductor (P-SSHI) technique, also known as bias flip circuit[1]. The circuit is implemented with 0.25 μm CMOS high voltage process with only 0.9648 mm chip area. Post-layout simulation of the circuit shows the circuit extracts 336% more pow...

This paper proposes a gate driver integrated circuit to prevent breakdown of switching power amplifiers. The proposed circuit consists of a dead-time generator, level shifters, and a breakdown blocker. The dead-time generator makes non-overlapped input signals and the breakdown blocker detects instantaneous turned-on input signals and resets them to the off-state before the switching power cell...

Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip by Shawn A. Phillips Chair of the Supervisory Committee: Professor Scott Hauck Electrical Engineering As technology scales, engineers are presented with the ability to integrate many devices onto a single chip, creating entire systems-on-a-chip. When designing SOCs, a unique opportunity exists to add custom reconfigurable fabr...

Performance of high fan–in Domino circuits is degraded by technology scaling due to exponential increase in leakage. To improve the performance Current Comparison Domino (CCD) circuits are widely used. This work presents design of wide fan-in high performance current comparison domino circuits with goals of minimizing the power dissipation and propagation delay at 90nm and 45nm ultra deep submi...

In this work the effects of uniaxial mechanical stress on a pixel readout circuit are theoretically analyzed. It is the effects of mechanical stress on the in-pixel transistors do not arise at the output, when a correlated double sampling circuit is used. However, mechanical stress effects on the photodiode will directly appear at the readout chain output. Therefore, compensation techniques are...

As the VLSI feature size has already decreased below lithographic wavelength, the printability problem due to strong diffraction effects poses a serious threat to the progress of VLSI technology. A circuit layout with poor printability implies that it is difficult to make the printed features on wafers follow designed shapes without distortions. The development of Resolution Enhancement Techniq...

Electromigration (EM) of the interconnects is a key factor in determining the reliability of an integrated circuit, especially for the present-day IC with shrinking interconnect dimension. The simulation of the EM reliability of the interconnects is usually performed using the line-via structure at the EM test temperature (e.g. 300 oC).However, such simulation using the line-via structure may n...

The design of modern integrated circuits is overwhelmingly complicated due to the enormous number of cells in a typical modern circuit. To deal with this di culty, the design procedure is broken down into a set of disjoint tasks. Circuit layout is the task that refers to the physical realization of a circuit from its functional description. In circuit layout, a connection-list called netlist of...