the crossing number of a graph  is the minimum number of edge crossings over all possible drawings of  in a plane. the crossing number is an important measure of the non-planarity of a graph, with applications in discrete and computational geometry and vlsi circuit design. in this paper we introduce vertex centered crossing number and study the same for maximal planar graph.

Embedded system design is one of the most challenging tasks in VLSI CAD because of the vast amount of system parameters to fix and the great variety of constraints to meet. In this paper we focus on the constraint of low energy dissipation, an indispensable peculiarity of embedded mobile computing systems. We present the first comprehensive framework that simultaneously evaluates the tradeoffs ...

Existing techniques in high-level synthesis mostly assume a simple controller architecture model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. With the wider acceptanc...

The problem of proving that a propositional boolean formula is satisfiable (SAT) is one of the fundamental problems in computer science. The application of SAT solvers in VLSI CAD has become of major interest. The most popular SAT algorithms are based on the well known Davis-Putnam procedure. There, to guide the search, a branching rule is applied for selecting and assigning unassigned variable...

Many optimisation problems in circuit design, in the following also refereed to as VLSI CAD, consist of mutually dependent sub-problems, where the resulting solutions must satisfy several requirements. Recently, a new model for Multi-Objective Optimisation (MOO) for applications in Evolutionary Algorithms (EAs) has been proposed. The search space is partitioned into socalled Satisfiability Clas...

This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the arc...

Until recently, the use of hierarchies in CAD for VLSI has almost exclusively been restricted to layout and simulation problems. The paper describes representation and handling of design hierarchies in the MIMOLA design system, featuring RT-level synthesis, test program generation and retargetable code generation. A method of embedding these tools in a common design environment, providing acces...

With the growing complexity of VLSI designs, functional debugging has become a bottleneck in modern CAD flows. To alleviate this cost, various SAT-based techniques have been developed to automate bug localization in the RTL. In this context, dominance relationships between circuit blocks have been recently shown to reduce the number of SAT solver calls, using the concept of solution implication...

Timing analysis plays a vital role in chip design, which analyze whether a chip design meets the timing constraints. The main objectives of timing analysis are speed and accuracy. There are two engines for timing analysis namely Statistical Timing Analysis (STA) and Statistical Static Timing Analysis (SSTA). VLSI CAD has been gaining a lot of interest in both STA and SSTA. As technology continu...

Extending VLSI CAD with higher-order logic integrates formal veriication with synthesis. The be-neets of doing so are: 1) relating instruction-set descriptions to implementations, 2) designing at a higher level of abstraction than at the level of schematics, 3) verifying by proof, 4) reusing veriied parameterized designs, 5) automatically compiling designs in higher-order logic to parameterized...