As the compactness of system-on-chip (SoC) increase, it becomes striking to integrate dedicated test logic on a chip. Starting with a broad idea of test problems, this survey paper focus on “Chip” Built in Self-Test (BIST) study and its promotion for board and system-level applications. This paper gives brief informative review of Built-in Self-test (BIST) and its testing techniques. Recently B...

Reliability and robustness have been always important parameters of integrated systems. However, with the emergence of nanotechnologies reliability concerns are arising with an alarming pace. The consequence is an increasing demand of techniques that improve yield as well as lifetime reliability of today’s complex integrated systems. It is requested though, that the solutions result in only min...

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital progr...

This paper describes three new march tests for multiport memories. A read (or write) port in such a memory consists of an n-bit address register, an n-to-2n-bit decoder (with column multiplexers for the column addresses) and drivers, and a K -bit data register. This approach gives comprehensive fault coverage for both array and multiport decoder coupling faults. It lends itself to a useful BIST...

This paper describes an approach to hierarchical self tests by use of a test controller. As design for testability and Built-In Self Tests (BIST) at the board level are becoming increasingly important, research has been carried out on formulating test controllers to control test activities. In our approach, instead of providing a fixed test controller design, an automatic synthesis tool is deve...

We propose an autonomous, deterministic scan-BIST architecture that allows compact, precomputed test sets with complete fault coverage to be used for field testing. The use of such short test sequences is desirable in safety-critical systems since it reduces the error latency. It also reduces testing time and therefore allows periodic field testing to be carried out with low system downtime. We...

Transient Response Testing has been shown to be a very powerful and economical functional test technique for linear analogue cells in mixed-signal systems. Recently this work has been extended to non-linear analogue circuits by treating Transient Response Testing as a structural test technique and employing optimised and reduced fault sets that are derived from Inductive Fault Analysis and circ...

T-flip-flop implementation of the universal module (signature analyzer and test generator) for built-in self-test of mixed signal circuits is proposed and analyzed.

In this paper, a built-in self-test (BIST) procedure is proposed for testing and fault tolerance of molecular electronicsbased nanofabrics. The nanofabrics are assumed to include up to 10 devices/cm; this requires new test strategies that can efficiently test and diagnose the nanofabrics in a reasonable time. Our BIST procedure utilizes nanofabric components as small test groups containing test...

For the first problem, how to test a core, there are a number of solutions: (1) through ASIC functional test; (2) direct test application, while accessing core through I/O muxing; (3) test application through boundary scan or a collar register; (4) Built-In Self-Test (BIST); and (5) proprietary solutions. It should be remembered at all times that there is no one size fits all solution. A soluti...