Indirect branch prediction is a performance limiting factor for current computer systems, preventing superscalar processors from exploiting the available ILP. Indirect branches are responsible for 55.7% of mispredictions in our benchmark set, although they only stand for 15.5% of dynamic branches. Moreover, a 10.8% average IPC speedup is achievable by perfectly predicting all indirect branches....

Instruction prefetching can effectively reduce instruction cache misses, thus improving the performance. In this paper, we propose a prefetching scheme, which employs a branch predictor to run ahead of the execution unit and to prefetch potentially useful instructions. Branch prediction based (BP-based) prefetching has a separate small fetching unit, allowing it to compute and predict targets a...

A processor with an explicit dataflow instruction-set architecture may be able to achieve performance comparable to a superscalar RISC processor, even on serial code. To achieve this, the dataflow processor must support speculative operation, especially speculative branches, and a pipeline with bypassing for serial code. This paper outlines a set of mechanisms to implement speculative operation...

Accurate branch prediction is critical to performance; mispredicted branches mean that ten’s of cycles may be wasted in superscalar architectures. Architectures combining very effective branch prediction mechanisms coupled with modified branch target buffers (BTB’s) have been proposed for wide-issue processors. These mechanisms require considerable processor resources. Concurrently, the larger ...

There were several hypotheses that motivated this research project. First, we proposed that running multiple processes pollutes the history in branch predictors due to aliasing. This pollution decreases accuracy. Second, we argued that branch prediction accuracy can be improved over existing techniques by removing this aliasing. Specifically, the history table can be partitioned to allow each p...

Branch Prediction Analysis has been proposed as an attack method to obtain key bits from a cryptographic application. In this report, we put forth several solutions to avoid or prevent this attack. The reported countermeasures require only minimal hardware support that is commonly available in modern superscalar processors.

This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy consumption in the processor it is worthwhile to spend more power in the branch predictor if this results in more accurate predictions that improve running time. Two techniques, however, provide substantial reductions ...

In this paper we study statistical consistency of partial losses suitable for learning structured output predictors from examples containing missing labels. We provide sufficient conditions on data generating distribution which admit to prove that the expected risk of the structured predictor learned by minimizing the partial loss converges to the optimal Bayes risk defined by an associated com...

Instruction dependency introduced by conditional branch instructions, which is resolved only at run-time, can have severe performance impact on pipelined machines. A variety of strategies are in wide use to minimize this impact. Additional instruction-traffic generated by these branch-strategies can also have an adverse effect on the system performance. Therefore, in addition to the likely redu...

CGMT can exert significant influence on the design and implementation of branch prediction. In this paper, the design of several typical branch predictors such as bimodel, GShare and McFarling is examined and branch prediction performance is improved by making some decisions with the help of TPC-W benchmark concerning whether to share some data structures among multiple threads or not. For a ty...