In this work we introduce a novel approach to digit-serial/parallel multiplication. This general class of multipliers is based on shiftaccumulation which also makes the approach suitable for implementation of shift-accumulators in distributed arithmetic. As a variable in the design process, the maximal number of cascaded fulladders can be selected. Thus, it is possible to as a special case obta...

Efficient hardware implementations of arithmetic operations in the Galois field are highly desirable for several applications, such as coding theory, computer algebra and cryptography. Among these operations, multiplication is of special interest because it is considered the most important building block. Therefore, high-speed algorithms and hardware architectures for computing multiplication a...

Multiplication and Squaring functions are widely used in many real time applications. They form an integral part in implementation of many Digital Signal Processing, Digital Image Processing and Multimedia algorithms. The size and power consumption of a DSP chip is influenced by the multiplication and squaring architectures that are used. The aim of this paper is to propose a novel fixed width,...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, a new word-parallel bit-serial finite field multiplier using normal basis is presented. The proposed architecture takes w clock cycles to compute the product bits, where the value for w, 1≤w≤ m, can be arbitrarily selec...

A Parallel multiplier using approximate compressors are proposed in this paper. The two new approximate 4-2 compressors are proposes that the simplified compressors have better power consumption than the optimized 4-2 compressor existing designs. These approximate compressors are then used in the restoration module of a Parallel multiplier. Four different schemes for utilizing the proposed appr...

With the continuous development of big data and hardware computing platforms, deep learning has been substantially applied in many intelligent scenarios. Recent studies have shown that using low bit-width networks inference can effectively improve overall performance accelerator by reducing computational ability requirements while maintaining recognition accuracy accelerator. Among them, convol...

We discuss the design of a high performance constant coefficient multiplier on the Xilinx XC6200 FPGA. The dynamic reconfiguration capabilities of the device are used to allow the constant coefficient to be rapidly changed. The design also provides better performance and density than similar multipliers on state of the art conventional FPGA’s which require complete reconfiguration to change the...

This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density ParityCheck (LDPC) codes, and Reed-Solomon codes. A systematic low-complexity bit-parallel finite field multiplier design approach is proposed. This design approach is applicable to GF (2m) constructed by arbitrary irreducible polyno...