The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0:6 m CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.

The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) techniques to SoC design. We have implemented on a VLSI test chip three alternative solutions to fill the gap: an arbitrated bus, a switch, and a self-timed ring. Circuit details and various extensions of the basic rin...

A testing scenario in the sense of De Nicola and Hennessy is developed to measure the worst-case eeciency of asynchronous systems using dense time. For all three variants considered, it is shown that one can equivalently use discrete time; in the discrete versions, one variant coincides with an approach based on discrete time in Vog95b], and thus we can clarify the assumptions behind this appro...

In this paper, we present FASE (Faster Asynchronous Systems Evaluation), a tool for evaluating the worst-case efficiency of asynchronous systems. The tool is based on some well-established results in the setting of a timed process algebra (PAFAS: a Process Algebra for Faster Asynchronous Systems). To show the applicability of FASE to concrete meaningful examples, we consider three implementatio...

This paper defines the fault-tolerant mutual exclusion problem in a message-passing asynchronous system and determines the weakest failure detector to solve the problem. This failure detector, which we call the trusting failure detector, and which we denote by T , is strictly weaker than the perfect failure detector P but strictly stronger than the eventually perfect failure detector P . The pa...

We compare the expressive power of two automata-based finite-state models of concurrency. We show that Droste’s and Kuske’s coherent stably concurrent automata and Bednarczyk’s forward-stable asynchronous systems describe the same class of regular event structures. This connection subsumes a previous study by Schmitt which relates Stark’s trace automata to asynchronous systems. This work relies...

We propose a new type of canonical decision diagrams, which allows a more efficient symbolic state-space generation for general asynchronous systems by allowing on-the-fly extension of the possible state variable domains. After implementing both breadth-first and saturationbased state-space generation with this new data structure in our tool SmArT, we are able to exhibit substantial efficiency ...

This paper presents the design of a restartable crystal controlled clock. The clock generator is a critical component in a newly proposed blended design methodology which combines clockless and clocked subsystems and is a special case of a Globally Asynchronous Locally Synchronous (GALS) design strategy. The clock generator has been successfully implemented in the TSMC 0.25μm NWELL process, occ...

Abstract: The use of asynchronous sequential circuits has brought many advantages to system development, given the following examples:  Signal interface protocols (for example SCSI)  Asynchronous circuits are ideal for building modular systems. This modular structure enables a global system time checkup. The asynchronous circuits developed for high performance systems, for speeds up to 75 MHz...

ÐThis paper presents a solvable specification and gives an algorithm for the Group Membership Problem in asynchronous systems with crash failures. Our specification requires processes to maintain a consistent history in their sequences of views. This allows processes to order failures and recoveries in time and simplifies the programming of high level applications. Previous work has proven that...