The performance and hardware complexity of super-scalar architectures is hindered by conditional branch instructions. When conditional branches are encountered in a program, the instruction fetch unit must rapidly predict the branch predicate and begin speculatively fetching instructions with no loss of instruction throughput. Speculative execution has a high hardware cost, is limited by dynami...

BACKGROUND AND OBJECTIVE Over 165 million cases of shigellosis occur in the world each year, mostly in developing countries. Outbreaks of shigellosis are associated with poor sanitation, natural calamities, contaminated food and crowded living conditions. In late summer 2006, during the final stage of an outbreak of shigellosis at a vast region of Isfahan province, Naein & Ardestan, our laborat...

While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay mechanism that is more suited to superscalar processors. We then quantitatively compare the performance of our delayed branch mechanism with run-time branch prediction, in the...

life as an outstanding physician and a pioneer of laryngobrnochoesophascopy in Iran. He completed elementary school in Ardestan and high school in Isfahan and then enrolled at the Tehran School of Medicine, graduating in 1952. In due course, he continued his medical training in otolaryngology at the Amir Aalam educational wards, he went to the US to continue his post-graduate training in the up...

Complete right bundle-branch block with right axis deviation was seen in nine patients who did not have right ventricular hypertrophy, pulmonary disease, or extensive lateral myocardial infarction. Four patients had chronic block and five had acute myocardial infarction. This pattern was attributed to a coexisting block in the right branch and in the inferior division of the left branch. It fre...

We propose an alternative approach to branch resolution based on the earlier work on decoupled memory architectures. Branch decoupling is a technique to decouple a single instruction stream program into two streams. One stream is solely dedicated to resolving branches as early as possible (both the branch condition and the branch target). The resolved branch targets are consumed by the other co...