نتایج جستجو برای: all digital phase locked loop
تعداد نتایج: 2730969 فیلتر نتایج به سال:
Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. Supporting the highest bandwidth data rates among devices requires advanced clock management technology such as delay-locked loops (DLLs). The DLL circuitry allows for very precise synchronization of external and internal clocks. In this paper a low jitter and...
In this paper a new variety of the digitized version of an analog phase locked loop has been proposed in order to overcome the conditionally stable nature of a software controlled phase locked loop. Also the conventional need of a low pass filter to filter out the high frequency components at the output of a phase detector is avoided through the use of In-phase and Quadrature signals. MATLAB si...
The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the sign...
The fundamental design concepts for phase-locked loops implemented with integrated circuits are outlined. The necessary equations required to evaluate the basic loop performance are given in conjunction with a brief design example. NOTE This document contains references to obsolete part numbers and is offered for technical information only.
For high speed application, jitter is a problem to communication system, as it reduces the performance of overall circuitry. As jitter is a type of corruption that cannot be eliminated, reducing jitter is one way to help to improve the system performance. In this paper, we introduce some ways to reduce the jitter in phase-locked loop. Introduction Phase-Locked Loop, PLL, is widely used among th...
There are a number of high volume applications for DC motors that require precision control of the motor’s speed. Phase locked loop techniques are well suited to provide this control by phase locking the motor to a stable and accurate reference frequency. In this paper, the small signal characteristics, and several large signal effects, of these loops are considered. Models are given for the lo...
طراحی PLL دو حلقه ای مبتنی بر آشکارسازی فاز پنجرهای با سرعت قفل بالا، توان مصرفی و اسپور مرجع پایین
In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in t...
The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the performance of digital systems. In intra-system interfaces where both latency and bandwidth are important, source-synchronous parallel channels have been adopted as the most effective solution. This work investigates receiver and clocking circuit design techniques for increasing the signalling rate a...
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