We introduce multi-edge type LDPC codes, a generalization of the concept of irregular LDPC codes that yields improvements in performance, range of applications, adaptability and error floor. The multiedge type LDPC codes formalism includes various constructions that have been proposed in the literature including, among others, concatenated tree (CT) codes [1], (generalized irregular) repeat acc...

42 JANUARY 2004 1053-5888/04/$20.00©2004IEEE e consider the problem of designing unoriented bipartite graphs with large girth. These graphs are the Tanner graphs associated with the parity-check matrix H of low density parity-check (LDPC) codes or Gallager codes. Larger girth improves the computational and bit error rate (BER) performance of these codes. The article overviews several existing m...

In this letter, we propose an appealing class of nonbinary quasi-cyclic low-density parity-check (QC-LDPC) cycle codes. The parity-check matrix is carefully designed such that the corresponding generator matrix has some nice properties: 1) systematic, 2) quasi-cyclic, and 3) sparse, which allows a parallel encoding with low complexity. Simulation results show that the performance of the propose...

Irregular repeat-accumulate Root-Check LDPC codes based on Progressive Edge Growth (PEG) techniques for block-fading channels are proposed. The proposed Root-Check LDPC codes are both suitable for channels under F = 2, 3 independent fadings per codeword and for fast fading channels. An IRA(A) Root-Check structure is devised for F = 2, 3 independent fadings. The performance of the new codes is i...

An orbital angular momentum (OAM) based LDPC-coded modulation scheme suitable for use in FSO communication is proposed. We demonstrate that the proposed scheme can operate under strong atmospheric turbulence regime and enable 100 Gb/s optical transmission while employing 10 Gb/s components. Both binary and nonbinary LDPC-coded OAM modulations are studied. In addition to providing better BER per...

Area and Energy Efficient VLSI Architectures for Low -Density Parity-Check Decoders Using an On-the-Fly Computation. (December 2006) Kiran Kumar Gunnam, M.S., Texas A&M University Co-Chairs of Advisory Committee: Dr. Gwan Choi Dr. Scott Miller The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. T...

Low density parity check (LDPC) codes are error-correcting codes that offer huge advantages in terms of coding gain, throughput and power dissipation in digital communication systems. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However,traditional hardware implementation of LDPC decoders require large am...

OFDM with quadrature amplitude modulation (QAM) technique can be used for high speed optical applications. Increasing the order of modulation, the bit error rate (BER) increases. Forward Error correction (FEC) coding like LDPC coding is generally used to improve the BER performance. LDPC provides large minimum distance and also the power efficiency of the LDPC code increases significantly with ...

We study the performance of binary spatiallycoupled low-density parity-check codes (SC-LDPC) when used with bit-interleaved coded-modulation (BICM) schemes. This paper considers the cases when transmission takes place over additive white Gaussian noise (AWGN) channels and Rayleigh fast-fading channels. The technique of upper bounding the maximum-a-posteriori (MAP) decoding performance of LDPC c...