This paper presents a model for characterizing delay and power for CMOS logic cells that accounts for input slope and output capacitance loading. A method for deriving the model parameters and VHDL modeling for simple logic gates is presented. The model makes feasible delay and power estimation at VHDL simulation speed, the errors of the model prediction are less than 5% of Spice results.

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be challenge to design high performance low-power systems. Therefore, designers are trying reduce dissipation these systems by using optimization techniques. Different mathematical operations can found the archit...

When a design reaches the register transfer level, essential architectural decisions have been taken; their validation required extensive simulation of the abstract behavioral specifications. The recognized need for formal verification cannot be met by current automatic equivalence and model checking tools, which mainly apply to logic synthesis inputs and outputs, or require manual abstraction....

In this Paper we present the hierarchical designs methodologies for integrated Circuits (IC) for a Very Large Scale Integration (VLSI) using free CAD tools Alliance. Alliance allow us to capture our digital designs through a hardware description language VHDL. Unlike the small digital systems which complete description can be included in a single VHDL file, the ICs designs for a medium and larg...

This paper presents VHDL-AMS model of an automotive vibration isolation seating system with an active electromechanical actuator. Five control algorithms for the actuator are implemented and their efficiencies are investigated by subjecting the system to a number of stimuli, such as a single jolt or noisy harmonic excitations. Simulations were carried out using the SystemVision simulator and re...

Modelica provides intuitive constructs to create and group model definitions. However, models themselves do not compose. In other words, the connection of type-compatible and locally balanced submodels does not generally yield a valid (e.g., balanced, structurally non-singular) model. Starting from simple examples of such invalid models (resulting from commonly encountered situations when using...