This paper presents the HW/SW co-design of a reconfigurable IP video surveillance and control system based on low cost Xilinx Spartan 3E FPGA family. The system allows users to observe video images captured by a camera via any standard browser and control remote devices. Our design focuses on the design of the HW base line JPEG encoder on FPGA and the design of a SW web server running on uCLinu...

SUMMARY A processing system with multiple field programmable gate array (FPGA) cards is described. Each FPGA card can interconnect using six I/O (up, down, left, right, front, and back) terminals. The communication network among FPGAs is scalable according to user design. When the system operates multi-dimensional applications, transmission efficiency among FPGA improved through user-adjusted d...

FPGAs have become quite popular for implementing digital circuits and systems because of reduced costs and fast design cycles. This has led to increased complexity of FPGAs, and with technology scaling, many new challenges have come up for the FPGA industry, leakage power being one of the key challenges. The current generation FPGAs are being implemented in 90nm technology, therefore, managing ...

This paper describes the reconfigurable implementation of a digital filter in an FPGA device. The filter implemented is a Laplacian filter which is used in DSP and image processing applications. For an efficient FPGA implementation of the filter, distributed arithmetic techniques were used. For a run-time reconfigurable implementation, the JBits SDK was used, which allows partial reconfiguratio...

This document describes the use of the FPGA coprocessor microEnable as Read Out Buffer (ROB) hardware for the trigger system of the Atlas detector. It shows with performance measurements the possibilities of FPGA hardware to buffer and manipulate data received from the detector very fast. It points out that FPGA hardware can be used successfully in the Atlas trigger environment.

This paper presents the architecture and implementation of a real time adaptive NLMS filter for nonstationary noise cancellation in a car environment.The active noise control techniques using adaptive digital filters are very much suitable and well proven.The proposed efficient Adaptive Noise Canceller is realized using Xilinx System Generator 12.3 on Spartan 3E FPGA. System Generator is a DSP ...

734 The JPEG standard is most widely used method of lossy compression for digital photography. In this paper, we will discuss the implementation of JPEG Encoder for FPGAs. The target device is a Stratix IV FPGA. The JPEG Encoder was synthesized and simulated using the Quartus FPGA design software at the clock frequency of 122.5 MHz. The design was tested on an image for different values of the ...

Existing FPGA architectures can be classified along two dimensions: reprogrammable vs. one-time programmable and general-purpose vs. domain specific. The most challenging class of FPGA architectures to design is the reprogrammable, general-purpose FPGA, of which Xilinx is the most wellknown example. In this paper we describe Triptych, a new FPGA architecture that addresses two problems of curre...

This document describes the evaluation of a 200MHz analogue-to-digital converter acquisition evaluation board. The evaluation board contains an AD9410 10-bit ADC [1], which was purchased from Analog Devices for $200. The evaluation board is interfaced via an Altera APEX FPGA to a custom capture card [2]. The APEX FPGA currently contains minimal logic for synchronizing the two data streams from ...

A Dynamic Instruction Set Computer (DISC) has been developed to support demand-driven instruction set mod-iication. Using partial reconnguration, DISC pages instruction modules in and out of an FPGA as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-speci...