Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to provide adequate performance is difficult because the overall delay characteristics are strongly dependent on the discharge patterns of internal gates. This paper proposes a methodology for sizing the sleep transistor for a large module base...

In this paper, an analytical model for a vertical double implanted metal-oxide semiconductor (DIMOS) transistor structure in 4H-Silicon Carbide (SiC) is presented. Simulation for transport characteristics of the SiC MOSFET with the exact device geometry is carried out using the commercial device simulator MEDICI. A rigorous experimental testing and characterization is done on a 4H-SiC DIMOS tra...

We predict theoretically and observe in experiment that the differential conductance of a superconducting SET transistor exhibits a peak which is a complete analogue in a macroscopic system of a standard resonant tunneling peak associated with tunneling through a single quantum state. In particular, in a symmetric transistor, the peak height is universal and equal to e/2πh̄. Away from the resona...

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A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor ...

Designing reliable systems becomes more difficult in recent years. Besides conventional problems such as transistor leakage, degradation and variation of transistor performance have severe impact on the dependability of VLSI systems[1]-[3]. In this paper, we deal with negative bias temperature instability (NBTI) which is one of the strongest reliability concerns for digital and analog CMOS circ...

A comprehensive modeling approach is applied to the study of pHEMT transistors for microwave power amplifier applications. This approach combines physical, electromagnetic and thermal simulations to model large power transistors used in these applications, allowing both the individual finger contribution and the global performance to be investigated in an efficient manner, which can be used wit...

We introduce a method to fabricate high-performance field-effect transistors on the surface of freestanding organic single crystals. The transistors are constructed by laminating a monolithic elastomeric transistor stamp against the surface of a crystal. This method, which eliminates exposure of the fragile organic surface to the hazards of conventional processing, enables fabrication of rubren...

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N-transi...