With growing interest in multiprocessor system-on-chip (SoC) designs and the increasing number of multicore designs at the high to medium end of the desktop and server markets, the question arises as to whether there should be convergence of the two concepts. This paper explores design principles for SoC multiprocessors and relates them to more general system requirements. It makes a case for f...

For manufacturers of microelectronic systems such as smart phones, tablets, and other mobile computing devices and for SoC (system-on-a-chip) designers, manufacturers, and vendors, system power consumption represents a major consideration. SoC designers must optimize power within SoC units, such as CPUs, graphic controllers, display controllers and memory controllers. However, on modern mobile ...

The use of fault-tolerant mechanism is essential to ensure the correct functionality of integrated circuits after manufacturing due to the massive number of faults that may occur during the process. In this work, we propose a set of fault-tolerant techniques to cope with faulty wires in Network-on-Chip (NoC). The most appropriate technique is chosen by taking into account the number of faulty w...

This paper proposed a system-on-chip (SOC) architecture for speech recognition which is speaker dependent. The feature extraction bases on LPC (linear predictive coefficient)-cepstrum coefficients, and template matching employs Hidden Markov Models (HMM). It does not aim to offer a sophisticated solution but rather a high speed solution. This SOC architecture includes an ASIC of LPC-cepstrum an...

The DFT and Test challenges faced, and the solutions applied, to the ARMl026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that will ultimately end up in many different environments. This core was instantiated into a test chip. The new DFT features were utilized successfully in the SOC.

Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories Johny Paul, Walter Stechele, Manfred Kröhnert, and Tamim Asfour 12:00 – 12:30 Position Paper & Discussion: Towards Actor-oriented Programming on PGAS-based Multicore Architectures Sascha Roloff, Frank Hannig, and Jürgen Teich 12:30 – 13:30 Lunch Break 13:30 – 14:30 Multi-Objective Diagnosis of Non-Permanent Faults in...

Network-on-chip-based multiprocessor systems-onchip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel platform involves scheduling the communication on the network-onchip. This paper presents different scheduling strategies that minimize resource usage by exploiting all scheduling freedom offered by networks-on-chip. It also int...

The augmentation of number of gates on chip makes SOC design more difficult. So we have to work on SOC design tools to make designer work easier and manage all the available gates. We propose an embedded Linux co-simulation with hardware simulation at a high level of abstraction (TLM) to verify the system very early in the design flow. This will allow to avoid return behind in the design flow.

The DFT and Test challenges faced, and the solutions applied, to the ARM1026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the challenges of distributing a DFT core solution that will ultimately end up in many different environments. This core was instantiated into a test chip. The new DFT features were utilized successfully in the SoC.

Ali Habibi, Ph.D. Concordia University, 2005 The advancement in the hardware area made it possible the integration of a complete yet complex system on a single chip (called System-on-a-Chip: SoC). Over 10 million gates, integrated together and running a real time optimized software red crossed classical design techniques. The payback of this advancement resides in the challenge facing SoC desig...