The field programmable gate array (FPGA) market is expanding because FPGAs enable faster development times and lower development costs than mask programmable gate arrays (MPGAs).1) However, the conventional SRAM-based FPGA requires offchip, non-volatile PROMs to store configuration data, which increases the total device cost and the board area. To provide a low-cost solution for field programma...

This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the c...

This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided  by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...

The RAMpage memory hierarchy is an alternative memory organization which addresses the growing CPU-DRAM speed gap, by replacing the lowest-level cache by an SRAM main memory. This paper presents some modifications to the RAMpage hierarchy. More aggressive first level cache implementations are shown to improve performance of the RAMpage model, when context switches were taken on misses to DRAM.

Memory devices are a prerequisite for today’s information technology. In general, two dif‐ ferent segments can be distinguished. Random access type memories are based on semicon‐ ductor technology. These can be divided into static random access memories (SRAM) and dynamic random access memories (DRAM). In the following, only DRAM will be consid‐ ered, because it is the main RAM technology for s...

When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of lowvoltage RAMs in terms of cell signal charge are clarified, ...

Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that ...

The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple...

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal–oxide–semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAM’s), dynamic random access memories (DRAM’s), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting ...