In any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forc...

In present VLSI technology energy dissipation is an important factor to be considered among other factors like area, speed and performance in portable devices. The size reduction and complexity of portable devices have resulted in large amount of power dissipation in the devices. As a result low power designs have become inevitable part of today’s devices. In this paper low power dissipation is...

Managing power and energy consumption has become a primary consideration for microprocessor design. This report examines the effect of technology scaling on static power and energy dissipation and evaluates three techniques to reduce static energy in primary and secondary microprocessor caches. We examine the energy and performance tradeoffs associated with each technique and present the leakag...

With semiconductor technology scaling approaching atomic limits, novel materials and physical phenomena are sought in order to realize new logic and memory devices. Spintronic devices offer intriguing avenues to improve digital circuits by leveraging nonvolatility to reduce static power dissipation and enable logic-in-memory approaches to computing. Novel hybrid spintronic-CMOS digital circuits...

T’fris paper introduces a two-port BiCMOS static memory cell that combines ECL-level word-linevoltageswingsandemitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access (CSEA) cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAM’S while preserving the high density and low power...

This paper presents the implementation of a 4-bit Arithmetic Logic Unit (ALU) using Complementary Energy Path Adiabatic Logic (CEPAL). This static adiabatic logic has proved its advantage through the minimization of the 1/2CVdd2 energy dissipation occurring every cycle. Firstly, the performance characteristics of CEPAL 4-to-1 multiplexer and full adder are compared against the conventional stat...

This paper introduces a two-port BiCMOS static mem-ory cell that combines ECL level word-line voltage swings andemitter-follower bit line coupling with a static CMOS latchto achieve access times comparable to those of high-speedbipolar SRAM's, while preserving the high density and lowpower of CMOS memory arrays. The memory can be ac-cessed for read and write independentl...

The Present day workstations, low-power processors, computers and super computers are using fast Static Random Access Memory (SRAMs) and will require, in the future, larger density memories with faster access time and minimum power consumption. Acknowledging the intense requirements for power, in current high performance memories of computing devices, the circuit designers have developed a numb...

Previous research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test effi...

Efficient temperature aware design in modern portable computers is becoming increasingly important. As technology moves into deep submicron feature sizes, the static or leakage power is expected to increase because of the exponential increase in leakage currents with technology scaling. Within die-process variation is increasing in nanometer technologies, it is observe that leakage power will b...