In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the ma...

This paper main intents to present a flying capacitor multilevel inverter based shunt active power filter(APF) with Sigma-Delta modulation. A multilevel Sigma-Delta modulation(SDM) control can be applied to control power section of APF intention to reducing sensitivity to flying capacitor voltage deregulation and mending modulator performance. In these control section of APF perfect harmonic ca...

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros recquired to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the hi...

This work develops an adaptive sigma–delta modulator that is based on adapting the quantizer step-size using estimates of the quantizer input rather than the modulator input. The adaptive modulator with a first-order noise shaping filter is shown to be bounded-input bounded-output stable. Moreover, an analytical expression for the signal-to-noise ratio is derived, and it is shown to be independ...

This paper presents the design of a monobit 6 order delta-sigma modulator in a GaAs 0.2 μm technology. The central frequency is 750 MHz and the sampling frequency is 3 GHz. The reached resolution is 10.5 bits over a 10 MHz bandwith. The modulator operates from ± 5 V power supplies and consumes 5.7 W. Each block of the modulator is presented at transistor level. Two drawbacks are pointed out: lo...

An architecture to simplify the circuit implementation of analog-to-digital (A/D) converter in a sigma-delta (ΣΔ) modulator is proposed. The two-step quantization technique is utilized to design architecture of ΣΔ modulator. The architecture is based on dividing the A/D conversion into two time steps for achieving resolution improvement without decreasing speed. The novel architecture is design...

This paper presents the study of an original closed-loop conditioning approach for fully-integrated convective inertial sensors. The method is applied to an accelerometer manufactured on a standard CMOS technology using an auto-aligned bulk etching step. Using the thermal behavior of the sensor as a summing function, a first order sigma-delta modulator is built. This “electrophysical” modulator...

The main purpose of this article is to offer some characterizations of $delta$-double derivations on rings and algebras. To reach this goal, we prove the following theorem:Let $n > 1$ be an integer and let $mathcal{R}$ be an $n!$-torsion free ring with the identity element $1$. Suppose that there exist two additive mappings $d,delta:Rto R$ such that $$d(x^n) =Sigma^n_{j=1} x^{n-j}d(x)x^{j-1}+Si...

approved: Pavan Kumar Hanumolu VCO-based ADCs have recently emerged as attractive alternative to conven­ tional Delta Sigma (ΔΣ) modulator architectures. Few salient features of a VCO­ based ADC are: 1) the quantization noise is 1 order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are ideally suited for oversampled data co...

In this paper a two stage bandpass MASH (multi-stage noise shaping) sigma-delta ( Σ∆ ) modulator is presented. A resolution of 14 bits has been achieved over a 5 MHz band around an intermediate frequency (IF) of 20 MHz with a clock frequency of 80 MHz. This performance is obtained using a 6-th order bandpass Σ∆ modulator followed by a 10 bit pipeline converter. The proposed circuit has been ext...