In a direct-conversion wireless receiver the baseband filter should be able to handle large blockers, resulting in a very challenging spurious free dynamic range (SFDR) requirement. In particular, the noise added in-band trades off with the linearity required to handle close out-of-band interferers [1]. Since the integrated noise generally is proportional to kT/C, once the noise floor for the f...

A 2-GHz, Continuous-Time Bandpass ∆Σ Analogto-Digital Converter sampled with a 40-GHz clock was implemented in a 130-nm SiGe BiCMOS technology. It achieves an SNDR of 55 dB and 52 dB over 60 MHz and 120 MHz, respectively, and an SFDR of 61 dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8-2 GHz. It employs a Gm-LCVAR filter based on a MOS-HBT cascode transconductor...

This paper presents modeling and simulation on the characteristics of semiconductor laser modulated within a strong optical feedback (OFB-)induced photon-photon resonance over a passband of millimeter (mm) frequencies. Continuous wave (CW) operation of the laser under strong OFB is required to achieve the photon-photon resonance in the mm-wave band. The simulated time-domain characteristics of ...

A compact OTA suitable for low-voltage active-RC and MOSFET-C filters is presented. The input stage of the OTA utilises the NMOS pseudo-differential amplifier with PMOS active load. The output stage relies upon the dual-mode feed-forward class-AB technique (based on an inverter-type transconductor) with common-mode rejection capability that incurs no penalty on transconductance/bias-current eff...

A time-interleaved ADC system is an effective way to implement a high-sampling-rate ADC with relatively slow circuits. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. Mismatches among channel ADCs degrade SNR and SFDR of the ADC system as a whole, and the effects of offset, gain and band...

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the p...

A radiation-hardened 12-bit non-linear DAC was designed and fabricated on Honeywell’s 0.35 μm MOI5 SOI CMOS process. The non-linear DAC allows a significant reduction in complexity and power dissipation when used within direct digital frequency synthesizers (DDFSs). The non-linear DAC implements a 32-segement piecewise linear approximation to sine function reducing the ROM look-up table size fr...

This paper proposes a 1.5 V 12-b CMOS ratio-independent algorithmic analog-to-digital converter (ADC) based on a capacitor-mismatch insensitive technique. A novel switched-capacitor multiplying digital-to-analog converter (MDAC) with an accurate gain of two is proposed for an algorithmic ADC. The proposed MDAC architecture requires only one opamp in four phases to generate the next residue outp...

This paper describes a 14-bit 2OMSPS switched-capacitor Stage Stae21t Sage N pipelined ADC that employs digital background calibration to N correct capacitor mismatch. The calibration concept is amenable to Digital correction Logic l_ Y implementation in SOC because it is digital in nature. The Digitalout calibration concept is demonstrated offline though in principle it can be included on-chip...

This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PW...