This paper presents an algorithm that compacts the Test Sequences generated by a GA-based ATPG program for sequential circuits. In this algorithm, from a set of test sequences, a properly selected subset of sequences is reordered and combined without reducing the number of detected faults. By introducing the metric of fault density sequence selection is guided towards sequences that have higher...

In this paper a new logic optimization method for sequential synchronous circuits is introduced. For this purpose the current main approaches, “Retiming and Resynthesis” and “Redundancy Addition and Removal” are considered. These techniques have some advantages and limitations that have been theoretically proven by several authors. The goal of the new optimization method is to combine these two...

In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the eeectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several IS-CAS89 sequential benchmark circuits using two diier-ent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, ...

The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles, both, data and control parts of the design in a uniform manner is proposed. The method combines deterministic and simulation-based techniques. On the register-transfer level, deterministic path activation is combined...

New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as well as the actual input vectors that attain such bounds. The initial state of the circuit is an important factor in determining the amount of switching activity in sequential circuits and is taken into account. A peak po...

In this paper a GA-based method that compacts Test Sequences for sequential circuits is presented. In this algorithm from an initial set of test sequences a subset of sequences is selected and from these sequences parts of them (subsequences) are selected which are reordered and combined into one sequence covering all faults detected by the initial set. The method exploits the presence of essen...

This paper is concerned with the question of automated test pattern generation for large synchronous sequential circuits and describes an approach based on Genetic Algorithms suitable for even the largest benchmark circuits, together with a prototype system named GATTO. Its effectiveness (in terms of result quality and CPU time requirements) for circuits previously unmanageable is illustrated. ...

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

All practical digital circuits are usually a mixture of combinational and sequential logic. Flip–flops are essential to sequential logic therefore fuzzy flip–flops are considered to be among the most essential topics of fuzzy digital circuit. The concept of fuzzy digital circuit is among the most interesting applications of fuzzy sets and logic due to the fact that if there has to be an ultimat...

It is known that a class of acyclic sequential circuits called balanced circuits can be tested by combinational ATPG. The first contribution of this paper is a modified and efficient combinational single fault ATPG method for any general (not necessarily balanced) acyclic circuit. Without inserting real hardware, we create a “balanced” ATPG model of the circuit in which all reconverging paths h...