Recently, a variety of robotic systems have been studied under the umbrella term of modular reconfigurable robotics [7,6]. Unlike conventional fixedmorphology robots, whose performance is usually confined by the operating environment and their own size, modular reconfigurable robots have the potential advantage of being able to change their morphology by rearranging the connectivity of their mo...

The H.264/AVC video coding standard features diverse computational hot spots that need to be accelerated to cope with the significantly increased complexity compared to previous standards. In this paper, we propose an optimized application structure (i.e. the arrangement of functional components of an application determining the data flow properties) for the H.264 encoder which is suitable for ...

Coarse grained reconfigurable processors have gained more popularity in the last years, as they introduce a new way for a dynamic and programmable execution similar to FPGA and tend to achieve the performance of application specific hardware. The reconfigurability on instruction level grants these architectures a big dynamicity and ability to embrace the diversity of the applications. Neverthel...

One of the most flexible and modular approaches to reconfigurable systems is a bus-based approach. In order to get realistic performance estimates of these systems, detailed modeling of the processor as well as the bus and memory hierarchy is required. In addition, when coupling one or more reconfigurable units with a superscalar, out-of-order issue, load/store RISC CPU using the on-chip system...

In this paper we present an area-efficient register transfer level technique for gracefully degradable data path synthesis called phantom redundancy. In contrast to spare-based approaches, phantom redundancy is a recovery technique that does not use any standby spares. Phantom redundancy uses extra interconnect to make the resulting data path reconfigurable in the presence of any (single) funct...

Reconfigurable equipment within a Software Defined Radio approach will be addressed on different levels: the control level, the resource level, and the operational level. A reconfiguration architecture and functionality will be introduced that offers interfaces to management entities and controls the internal components to select, negotiate and perform the appropriate reconfiguration actions. T...

In this thesis, we propose to use a reconfigurable processor as main computation element in embedded systems for applications from the multi-media and communications domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable Processing Unit (RPU). Many of our target applications require real-time signalprocessing of data streams and expose a high computational dema...

In this paper, a novel domain specific reconfigurable architecture and an associated design methodology which provides flexibility as well as autonomous restructuring of Processing Elements (PEs) of Virtual Reconfigurable Circuits (VRCs) is proposed. The proposed VRC and evolutionary algorithm is described in VHDL independently of a target platform i.e. as a soft IP core, and realized in the FP...