نتایج جستجو برای: quasi floating gate

تعداد نتایج: 145973  

2013
W. Widanarto

– A new type of NO2 gas sensor has been made using the Floating Gate Field Effect Transistor (FG-FET) sensor system. 200 nm ZnO films were deposited on Si/Ti/Pt electrodes, which are mounted on FG-FET chips. SEM and EDX characterization methods were employed to study the surface of these films. The change in the work function of the film due to their interaction with NO2 has been measured at va...

2016
Quoc An Vu Yong Seon Shin Young Rae Kim Van Luan Nguyen Won Tae Kang Hyun Kim Dinh Hoa Luong Il Min Lee Kiyoung Lee Dong-Su Ko Jinseong Heo Seongjun Park Young Hee Lee Woo Jong Yu

Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical sta...

Journal: :IEEE Transactions on Circuits and Systems I: Regular Papers 2017

1998
Fang-shi Lai Wei Hwang

In this paper, a new high-speed circuit technique called differential cascode voltage switch with pass-gate (DCVSPG) logic tree is presented. The circuit technique is designed using a pass-gate logic tree in DCVSPG instead of the nMOS logic tree in the conventional DCVS circuit, which eliminates the floating node problem. By eliminating the floating node problem, the DCVSPG becomes a new type o...

2002
John Hyde Todd Humes Chris Diorio Mike Thomas Miguel Figueroa

We describe a floating-gate trimmed, 14-bit, 250Ms/s current-steered DAC fabricated in a 0.25μm CMOS logic process. We trim the static INL to ±0.3LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm of die area, consumes 53mW at 250MHz, allows on-chip electrical trimming, and achieves 72dB SFDR at 250Ms/s. Introduction Emerging standards for communications systems requ...

1999
Paul E. Hasler Jeff Dugger

We study the weight dynamics of the floating-gate pFET synapse and the effects of the pFET’s gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltages. In particular, we want a rule of the form _ = + [ ], where is a voltage signal on the gate terminal an...

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