This article explains a new implementation of efficient D-Flip-Flop (DFF) using Gate-Diffusion-Input (GDI) technique, PowerPC, DSTC, and HLFF. This DFF design allows reducing power-delay product and area of the circuit, while maintaining low complexity of logic design. Performance comparison with other DFF design techniques is presented, with respect to gate area, number of devices, delay and p...

We observe that the state-of-the-art power-saving mechanisms (PSM) for IEEE 802.16e is neither optimal in terms of delay nor in terms of energy consumption. We propose a new PSM which achieves the optimality in terms of the average buffering delay without increasing energy consumption. In order to do so, we derive a formula which relates the average buffering delay to sleep intervals. Simulatio...

Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components...

Let G be a connected affine algebraic group and let X be a regular G-variety in the sense of [BDP] (recalled in Definition 2.2 below). The variety X contains an open orbit G/H whose complement D is a strictly normal crossing divisor in X. In this note we show the following vanishing result for rational equivariant Chern classes of the bundle of logarithmic differentials on the variety X: ci (Ω ...

One of the most promising solution for transport protocol over very high bandwidth-delay product networks is HighSpeed TCP. However, little is known about its performance as well as its interaction with other elements of the network (such as the RED queue management). In this paper, a comprehensive control-theoretic analysis of HighSpeed TCP is provided. We develop a fluid-flow model of the Hig...

Scaling TCP to very large bandwidth-delay product networks has proven to be very challenging. When diagnosing TCP behavior in these environments, we have found that monitoring various TCP parameters and visually correlating them with host and application information is a very effective analysis technique. In this paper we show how this technique can be implemented with a combination of the Web1...

In this paper a new design of full adder cell based on Sense Energy Recovery concept using novel exclusive NOR gates is presented. Low-power consumption and delay are targeted in implementation of our design. The circuit designed is optimized for low power at 0.18-μm and 0.09 μm CMOS process technologies in full custom environment. The new circuit has been compared to the existing work based on...

This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation result...

An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high thres...

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implemen...