نتایج جستجو برای: pipelining

تعداد نتایج: 1926  

Journal: :Theor. Comput. Sci. 2013
Nuno Santos André Schiper

Paxos is probably the most popular state machine replication protocol. Two optimizations that can greatly improve its performance are batching and pipelining. However, tuning these two optimizations to achieve high-throughput can be challenging, as their effectiveness depends on many parameters like the network latency and bandwidth, the speed of the nodes, and the properties of the application...

1998
R. Govindarajan Narasimha Rao Erik R. Altman Guang R. Gao

Instruction scheduling methods based on the construction of state diagrams (or automatons) have been used for architectures involving deeply pipelined function units. However, the size of the state diagram is prohibitively large, resulting in high execution time and space requirement, which in turn, restrict the use of these methods. In this paper, we develop the underlying theory for reducing ...

1994
Benjamin W. Wah

Two-level pipelining in processor arrays (PAs) involves pipelining of operations across processing elements (PEs) and pipelining of operations in functional units in each PE. Although it is an attractive method for improving the throughput of PAs, existing methods for generating PAs with two-level pipelining are restricted and cannot systematically explore the entire space of feasible designs. ...

Journal: :IEEE Trans. on CAD of Integrated Circuits and Systems 1995
Chuan-Hua Chang Edward S. Davidson Karem A. Sakallah

Aggressive design using level-sensitive latches and wave pipelining has been proposed to meet the increasing need for higher performance digital systems. The optimal clocking problem for such designs has been formulated using an accurate timing model. However, this problem has been difficult to solve because of its nonconvex solution space. The best algorithms to date employ linear programs to ...

Journal: :Periodica Polytechnica Electrical Engineering and Computer Science 2014

Journal: :IEEE Trans. Computers 2001
Glenn Reinman Brad Calder Todd M. Austin

ÐIn the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses, branch mispredictio...

2009
Juergen Ributzka Guang R. Gao

Current trends in high performance computing have produced two distinct families of chips. The first one is called complex core, which consists of a few, very architecturally sophisticated cores. The other chip family consists of many simple cores, which lack the advanced features of the complex ones. The two ideological camps have their examples in the current market. The Intel Core Duo family...

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